
Nikhil Joshi
M. Tech (VLSI Design) Major Courses: 1) FPGA Design(Verilog) (DE1/2/2-115 boards) (Modelsim,Quartus) 2) Digital IC Design 3) CAD for VLSI Design(Floorplanning, placement... | Bengaluru, Karnataka, India
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Nikhil Joshi’s Location Bengaluru, Karnataka, India
Nikhil Joshi’s Expertise M. Tech (VLSI Design) Major Courses: 1) FPGA Design(Verilog) (DE1/2/2-115 boards) (Modelsim,Quartus) 2) Digital IC Design 3) CAD for VLSI Design(Floorplanning, placement and routing, clock tree synthesis) 4) IC Technology 5) ASIC Design (1 project following ASIC flow on Cadence NCLAUNCH, RC Compiler, Encounter) 6) Scripting and Verification (PERL/TCL) 7) Low Power IC Design 8) VLSI Testing and Testability 9) Memory Design and Testing (March c patters etc) 10) Analog IC/ Mixed Signal IC Design 11) VLSI Digital Signal Processing Major Projects: 1) M.Tech Thesis: 3D Clock Distribution Network Design with TSV Count Optimization Clock tree design in MATLAB and validation in NGSPICE 2) ASIC Design of Adder, ROM and MUX based Distributed Arithmetic Architecture Design (DAA) 3) Low Power and High Speed SRAM Memory architecture with Cache Miss Period Minimization
Nikhil Joshi’s Current Industry Samsung Semiconductor
Nikhil
Joshi’s Prior Industry
Sensight Technologies
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Synopsys
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Samsung Semiconductor
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Work Experience

Samsung Semiconductor
Senior Staff Engineer (Rtl Design)
Sat Jun 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Asic Design Engineer
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Sensight Technologies
Design Engineer
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)