
Nikhil Patel
- 8.9 years of VLSI industry experience in ASIC Physical Design. - Experience in Place & Route, Static... | Bengaluru, Karnataka, India
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Nikhil Patel’s Emails ni****@ei****.com
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Nikhil Patel’s Location Bengaluru, Karnataka, India
Nikhil Patel’s Expertise - 8.9 years of VLSI industry experience in ASIC Physical Design. - Experience in Place & Route, Static Timing Analysis, Physical Verification, Signal Integrity analysis, Low power technique implementation and validation, ECO Implementation, Hierarchical design Implementation. - Good Knowledge of ASIC design flow from Netlist to GDSII. - Good knowledge of TCL - Worked on 40nm, 28nm,16nm,14nm,10nm and 7nm technology nodes projects. - Tool skill: Cadence EDI/INNOVUS, Magma Talus, Synopsys IC Compiler, Mentor’s Calibre, Synopsys’ Primetime, Synopsys’ Star-RC, Apache RedHawk, Conformal LEC for formal verification, Synopsys’s IC Compiler II
Nikhil Patel’s Current Industry Marvell Technology
Nikhil
Patel’s Prior Industry
Einfochips
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Intel
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Synapse Design
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Innovium
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Marvell Technology
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Work Experience

Marvell Technology
Senior Staff Engineer
Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Marvell Technology
Staff Engineer
Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Innovium
MTS
Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Synapse Design
Module Lead
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Consultant (Physical Design Engineer)
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Synapse Design
Senior Physical Design Engineer
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Senior Physical Design Engineer
Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Engineer
Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Project Trainee
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)