Nirav Patel
I am an aspiring Electrical Engineer, graduate form San Jose State University specializing in digital VLSI/SOC/ASIC design and... | San Francisco, San Francisco, United States
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Nirav Patel’s Emails ni****@ju****.net
Nirav Patel’s Phone Numbers No phone number available.
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Nirav Patel’s Location San Francisco, San Francisco, United States
Nirav Patel’s Expertise I am an aspiring Electrical Engineer, graduate form San Jose State University specializing in digital VLSI/SOC/ASIC design and verification. I have worked on multiple project on RTL design and verification. Skills/Tools: Methodology: UVM HDL: Verilog, System Verilog. Programming: C, C++, Python, and Perl Tools: Synopsys VCS, Synopsys Prime Time, Synopsys Design Compiler, and NCVerilog. Concepts: UVM test bench. Development, System Verilog Assertion ,System Verilog constraints, Computer Architecture.
Nirav Patel’s Current Industry Juniper Networks
Nirav
Patel’s Prior Industry
Seagate Technology
|
San Jose State University
|
Juniper Networks
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Work Experience
Juniper Networks
ASIC Engineer 2
Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
San Jose State University
Instructional Student Assistant
Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Student
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Seagate Technology
Engineering Technician
Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Nirav Patel Email Addresses
FAQ About Nirav Patel
-
Nirav Patel is located at
San Francisco, San Francisco, United States -
Nirav Patel is a
I am an aspiring Electrical Engineer, graduate form San Jose State University specializing in digital VLSI/SOC/ASIC design and verification. I have worked on multiple project on RTL design and verification. Skills/Tools: Methodology: UVM HDL: Verilog, System Verilog. Programming: C, C++, Python, and Perl Tools: Synopsys VCS, Synopsys Prime Time, Synopsys Design Compiler, and NCVerilog. Concepts: UVM test bench. Development, System Verilog Assertion ,System Verilog constraints, Computer Architecture. Juniper Networks -
Nirav Patel currently works in the
Juniper Networks -
Nirav Patel specializes in
I am an aspiring Electrical Engineer, graduate form San Jose State University specializing in digital VLSI/SOC/ASIC design and verification. I have worked on multiple project on RTL design and verification. Skills/Tools: Methodology: UVM HDL: Verilog, System Verilog. Programming: C, C++, Python, and Perl Tools: Synopsys VCS, Synopsys Prime Time, Synopsys Design Compiler, and NCVerilog. Concepts: UVM test bench. Development, System Verilog Assertion ,System Verilog constraints, Computer Architecture. -
Nirav Patel speaks the following languages:
No languages available. -
Nirav Patel has prior experience in the following industries:
San Jose State University , San Jose State University , Seagate Technology -
Nirav Patel has the following professional experience:
Juniper Networks , San Jose State University , San Jose State University , Seagate Technology . -
You can view Nirav Patel’s
LinkedIn profile at LinkedIn URL. -
Nirav Patel’s work email addresses are
[email protected] . -
Nirav Patel works at
Juniper Networks
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