
Nirmalraj Mohanraj
Responsibilities include : Block and SoC Level Verification planning and review Block and SoC Environment development (SV/UVM) Directed/constraint-random test generation Covergroup development,... | Austin, Texas, United States
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Nirmalraj Mohanraj’s Emails nm****@am****.com
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Nirmalraj Mohanraj’s Location Austin, Texas, United States
Nirmalraj Mohanraj’s Expertise Responsibilities include : Block and SoC Level Verification planning and review Block and SoC Environment development (SV/UVM) Directed/constraint-random test generation Covergroup development, Coverage analysis and closure Verification Plan/Report documentation Technical Skills: EDA Tools: Cadence – Incisive Simulator, SimVision, Incisive Metrics Center, Mentor – QuestaSim, QuestaVIP, UVM Framework, inFact, Visualizer UVM Debug Environment, Verification Run Management Synopsys – VCS Programming Languages: C, C++ HDL/HVL: Verilog, SystemVerilog Certifications: Doulos UVM Adopter Class Verification Methodologies: Universal Verification Methodology (UVM) Protocols: AMBA AHB, APB, I2C, SPI, UART Scripting Languages: PERL, Python, SHELL Other Tools: MATLAB, SVN, Cliosoft
Nirmalraj Mohanraj’s Current Industry Amd
Nirmalraj
Mohanraj’s Prior Industry
Orora Design Technologies
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On Semiconductor
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Mythic
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Amd
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Work Experience

Amd
Member Of Technical Staff
Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mythic
Staff Digital Design Verification Engineer
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Mythic
Senior Digital Design Verification Engineer
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
On Semiconductor
Senior Design/Verification Engineer
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
On Semiconductor
System IP Design/Verification Engineer
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Orora Design Technologies
Circuit Modelling Intern
Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)