
Nithin Pradeep
Innovative and self-motivated Design Verification Engineer with a proven record of accomplishments in the areas of Simulation (UVM)... | Austin, Texas, United States
*50 free lookup(s) per month.
No credit card required.
Nithin Pradeep’s Emails ni****@si****.com
Nithin Pradeep’s Phone Numbers No phone number available.
Social Media
Nithin Pradeep’s Location Austin, Texas, United States
Nithin Pradeep’s Expertise Innovative and self-motivated Design Verification Engineer with a proven record of accomplishments in the areas of Simulation (UVM) Based as well as Formal Based Verification techniques. Core Qualifications: • Profound knowledge of RTL designing involving Verilog/System Verilog. • Good experience with high-speed digital circuit design (schematic entry, layout, DRC/LVS). • Excellent programming skills in HDL (System Verilog). • Adept in utilizing EDA tools (Cadence Indago, Cadence Xcellium, Questa Simvision, Synopsys VCS). • Proficient in implementing software solutions using (Python,Perl,C++,MATLAB). • Experience in writing Test benches in System Verilog. • Excellent knowledge in verification methodologies including both UVM and Formal. • Experienced in working on Unix systems. • Excellent written and verbal communication skills. Skills: • Hardware description Languages: Verilog HDL. • Programming Languages: C and C++. • Scripting Languages: Shell(bash), Perl, Python, Ruby. • Assembly Languages: Intel 8085, PIC. • Formal Tools: Questa Formal Apps and Cadence Jaspergold. • Simulation Tools: Cadence Xcellium, Cadence Indago, Questa Simvision and Synopsys Verdi • Hardware Verification Languages: System Verilog, System Verilog RNM, SVA, Specman • Hardware Verification Methodologies: UVM Based Verification, Formal Verification • Synthesizers: Synopsys Design Compiler, Xilinx Implementation Tools. • Circuit Layout Tools: Cadence Virtuoso Layout Editor, Spectre. • Scientific Programs and Languages: MATLAB, Mathematica. • Word Processing: MS-Word, Latex. Operating Systems: Windows, Unix/Linux Specialties: Digital VLSI, RTL, Verification, Gate Level Simulations, Logic Design, Static Timing Analysis,DRC/LVS, MIPS Processor, SPICE, CPU, Architecture, Hardware, EDA design, Reconfigurable Computing, Design Automation, Tool Flows Enablement.
Nithin Pradeep’s Current Industry Microsoft
Nithin
Pradeep’s Prior Industry
Atkins
|
Silicon Labs
|
Samsung Semiconductor
|
Microsoft
Not the Nithin Pradeep you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Microsoft
Senior Design Verification Engineer
Thu Aug 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung Semiconductor
Senior Design Verification Engineer
Thu Dec 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Silicon Labs
Design Verification Engineer
Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Silicon Labs
Design Verification Intern
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Atkins
Design Engineer
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Atkins
Graduate Engineer
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)