
Parth Chaudhari
Working Full Time as a CPU Physical Design Engineer within the Cores Group at AMD: ▪ Independently drive full,... | San Francisco, California, United States
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Parth Chaudhari’s Location San Francisco, California, United States
Parth Chaudhari’s Expertise Working Full Time as a CPU Physical Design Engineer within the Cores Group at AMD: ▪ Independently drive full, semi-custom and/or synthesized block design and coordinate the associated integration into a microprocessor environment. ▪ Interact closely with the micro-architecture, RTL, verification, and CAD design teams. ▪ Perform electrical, logical, and timing verification of designs. ▪ Integrate designs with CPU logic and various power requirements. ▪ Perform circuit/logic specification, schematic entry, timing analysis (Primetime), power estimation, logical/electrical/physical checks, block reviews and documentation. ▪ Write Perl and TCL scripts to aid design automation and debugging. ▪ Work closely with methodology and floor plan teams to set up design constraints for upcoming project. ▪ Assist in testing out new SAPR (synthesis and automated place and route e.g. Design Compiler and IC Compiler) flows during high level design phase. ▪ Experiment with various full chip floor plan options and structural placement of flop/latch arrays and hard macros in the tiles Fields of Interest: ▪ High Performance CPU Physical Design ▪ FloorPlanning, Place & Route, CTS & Timing Closure ▪ Synopsys Tools: IC Compiler, ICC2, Primetime. Cadence Tools: Virtuoso, Encounter ▪ CPU Microarchitecture, GPU Compute, Microservers, Low Power Design, Scalable Power Architectures, Multithreaded Designs Products: ▪ AMD Excavator Core [CPU] ▪ AMD Zen3 Core [CPU] ▪ AMD Zen4 Core [CPU] ▪ Working on the next generation X86 & ARM Cores
Parth Chaudhari’s Current Industry Amd
Parth
Chaudhari’s Prior Industry
Skylark Circuits
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Siemens
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University Of Minnesota
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Lsi
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Amd
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Work Experience

Amd
MTS CPU Physical Design Engineer at AMD
Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amd
Senior CPU Physical Design Engineer
Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
CPU Physical Design Engineer
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Intern, Processor Solutions
Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Minnesota
Graduate Student
Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Siemens
Intern
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Skylark Circuits
Summer Intern
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)