
Parthajit Bhattacharya
I am leading and managing a team of engineers involved in developing software solutions for cutting edge DFT/ATPG... | Bengaluru, Karnataka, India
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Parthajit Bhattacharya’s Emails pa****@me****.com
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Parthajit Bhattacharya’s Location Bengaluru, Karnataka, India
Parthajit Bhattacharya’s Expertise I am leading and managing a team of engineers involved in developing software solutions for cutting edge DFT/ATPG solutions. Mentoring engineers to achieve their full potential and solve complex problems faced by our customers. Managing complete software development cycles of software products that are generating revenue in millions of USD. I have been architecting and developing software since last 20 years in various areas or VLSI CAD / EDA. Had the opportunity to work on areas like ATPG, Diagnosis, DFT, Timing optimization, Signal Integrity optimization, VLSI-Test Compression, low pin VLSI test. Formal verification, EDA tool infrastructure, LEF/DEF etc. Have worked on major VLSI CAD companies as an engineer, a technical lead and now managing a team along with continued technical contributions. Built team from ground up, recruiting, mentoring and training and solved various customer issues and contributed towards customer success. Innovated technologies related to VLSI test optimizations, and in the process filed and was granted five US patents, published three papers in various conferences. Well versed in programming with C/C++, Tcl, Peard, shell script. Have knowledge and self-trained on ML, Deep Learning. And used these tools to improve some of the VLSI CAD algorithms. Lifelong learner, lively, approachable and people find me humorous.
Parthajit Bhattacharya’s Current Industry Synopsys
Parthajit
Bhattacharya’s Prior Industry
Nerist
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Mentor Graphics
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Sequence Design
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Cadence Design Systems
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Synopsys
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Work Experience

Synopsys
Director, R&D
Sun May 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Sr. R&D Manager
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Sr. Staff R&D Engineer
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Staff R&D Engineer
Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Sr. R&D Engineer
Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Member Consulting Staff (Mcs)
Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Sequence Design
Smts
Mon Sep 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Mentor Graphics
Mts
Sat Dec 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Nerist
Guest Lecturer
Tue Sep 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)