
Parvinder Singh
Having 9+ years of work experience in the EDA/ESL domain. Having experience of creating performance models for architecture... | Delhi, Delhi, India
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Parvinder Singh’s Emails pa****@sy****.com
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Parvinder Singh’s Location Delhi, Delhi, India
Parvinder Singh’s Expertise Having 9+ years of work experience in the EDA/ESL domain. Having experience of creating performance models for architecture exploration use case using SystemC and TLM2.0. Worked on creating various modules from scratch which includes writing down specification to the production of the module for architecture exploration use cases. Good knowledge of various coherency protocols handling coherent interconnect and different level of cache controller blocks. Created various transactor for the different protocol at various abstraction level for different use cases like Co-simulation, performance exploration, and functional verification Worked on creating Functional model for software validation use case using SystemC and TLM2.0 Specialties: Bus modeling with TLM2.0, Interconnect, SystemC, Knowledge of ARM FM Bus Protocols: AXI4, AXI3 ACE-Lite, ACE, CHIB, and C, APB Tools: Synopsys PA tools for architecture exploration (PA-MCO), VPA (for virtual platforms), TLMC, Virtualizer Studio Scripting Languages: TCL, Perl Languages: C, C++, SystemC, TLM2.0, Also have some basic knowledge of the hardware language (VHDL/Verilog).
Parvinder Singh’s Current Industry Nvidia
Parvinder
Singh’s Prior Industry
Synopsys
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Circuitsutra
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Texas Instruments
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Nvidia
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Work Experience

Nvidia
Sr Architect
Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Sr R&D Engineer 2
Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Sr. Member Of Technical Team
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Sr. Rnd Engineer
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
R & D Engineer Level2
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Circuitsutra
Member Of Technical Staff
Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Contractor
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Circuitsutra
Soc Modelling Engineer
Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Circuitsutra
Soc Modelling Engineer
Mon Nov 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Senior Member of Technical Team
— Present