Patrick Lin

Patrick Lin

20+ years SOC Design Integration & Front-end Experience System Level Architecture Planning and Analysis First n16 FinFET Test Chip Integrator... | Taiwan

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Work Experience

Hewlett Packard Enterprise

Master Technologist

Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Hewlett Packard Enterprise

Expert

Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Kneron

Senior Staff Engineer

Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Cisco

Technical Leader

Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Mediatek

Technical Manager

Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Genesyslogic

Technical Manager

Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Via Technologies

Engineer

Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)

Hewlett Packard Enterprise

Master Technologist

— Present

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