
Peter Cheng
Power IC product development from product definition to silicon design to release. Full NPI flow. Manage new product development... | Cupertino, California, United States
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Peter Cheng’s Emails pe****@gl****.com
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Peter Cheng’s Location Cupertino, California, United States
Peter Cheng’s Expertise Power IC product development from product definition to silicon design to release. Full NPI flow. Manage new product development by leveraging on multiple technical functional groups to work as a team. Business management including product pricing strategy and tradeoff and revenue. Responsible for the following products: Computer Platform Power Stage, Switching Regulators, Type C USB Port Protection Switches, eFuse, CPU Multi-Phase Controller.
Peter Cheng’s Current Industry Globalfoundries
Peter
Cheng’s Prior Industry
Tegal
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Integrated Sensor Solutions
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Elantec Semiconductor
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Intersil
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Alpha And Omega Semiconductor
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Atmel
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Magnachip Semiconductor
|
Transphorm
|
Globalfoundries
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Work Experience

Globalfoundries
Director
Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Transphorm
Executive. Product Marketing and Applications
Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Alpha And Omega Semiconductor
Senior Director Power IC Product Line
Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Magnachip Semiconductor
Senior Marketing Manager, SMS Marketing
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Atmel
Director of Engineering, Analog Power
Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Alpha And Omega Semiconductor
Director of Design
Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intersil
Lead Design Engineer
Sun Sep 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Elantec Semiconductor
Senior Design Engineer
Sun Mar 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Integrated Sensor Solutions
Senior Design Engineer
Mon Aug 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Tegal
Field Service Engineer
Tue Sep 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time)