Piotr Bajorowicz
Specialities: FPGA emulation, Verification IP's, SCE-MI transactors, Design Verification Technologies: Xilinx Virtex 5, Xilinx Virtex 7, Xilinx Virtex UltraScale Computer... | Katowice, Śląskie, Poland
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Piotr Bajorowicz’s Emails pi****@al****.com
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Piotr Bajorowicz’s Location Katowice, Śląskie, Poland
Piotr Bajorowicz’s Expertise Specialities: FPGA emulation, Verification IP's, SCE-MI transactors, Design Verification Technologies: Xilinx Virtex 5, Xilinx Virtex 7, Xilinx Virtex UltraScale Computer languages: C/C++, SystemVerilog, UVM, VHDL, Tcl, bash/tcsh, GNU Make, Perl, Python Tools: HES-DVM, Riviera-PRO, Modelsim/Questa, Synplify Premier, Xilinx Vivado, LabView, GNU GCC Communication protocols: AXI, AHB, Ethernet Version Control: GIT
Piotr Bajorowicz’s Current Industry Synaptics
Piotr
Bajorowicz’s Prior Industry
Aldec
|
Synaptics
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Work Experience
Synaptics
IC Verification Engineer
Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Aldec
Senior Application Engineer
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Aldec
FPGA Emulation Support Engineer
Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Piotr Bajorowicz Email Addresses
FAQ About Piotr Bajorowicz
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Piotr Bajorowicz is located at
Katowice, Śląskie, Poland -
Piotr Bajorowicz is a
Specialities: FPGA emulation, Verification IP's, SCE-MI transactors, Design Verification Technologies: Xilinx Virtex 5, Xilinx Virtex 7, Xilinx Virtex UltraScale Computer languages: C/C++, SystemVerilog, UVM, VHDL, Tcl, bash/tcsh, GNU Make, Perl, Python Tools: HES-DVM, Riviera-PRO, Modelsim/Questa, Synplify Premier, Xilinx Vivado, LabView, GNU GCC Communication protocols: AXI, AHB, Ethernet Version Control: GIT Synaptics -
Piotr Bajorowicz currently works in the
Synaptics -
Piotr Bajorowicz specializes in
Specialities: FPGA emulation, Verification IP's, SCE-MI transactors, Design Verification Technologies: Xilinx Virtex 5, Xilinx Virtex 7, Xilinx Virtex UltraScale Computer languages: C/C++, SystemVerilog, UVM, VHDL, Tcl, bash/tcsh, GNU Make, Perl, Python Tools: HES-DVM, Riviera-PRO, Modelsim/Questa, Synplify Premier, Xilinx Vivado, LabView, GNU GCC Communication protocols: AXI, AHB, Ethernet Version Control: GIT -
Piotr Bajorowicz speaks the following languages:
No languages available. -
Piotr Bajorowicz has prior experience in the following industries:
Aldec , Aldec -
Piotr Bajorowicz has the following professional experience:
Synaptics , Aldec , Aldec . -
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Piotr Bajorowicz’s work email addresses are
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Piotr Bajorowicz works at
Synaptics
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