Prashanth Sakthi

Prashanth Sakthi

Experienced Strategist with a demonstrated history of working in the semiconductors industry. Strong business development professional skilled in... | Portland, Oregon, United States

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Work Experience

Intel

Director - Process Product Pathfinding

Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Program Manager - Competitive Assessment & Platform Enabling Strategy

Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Engineering Manager - Design system & IP

Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Program Manager - Wearable & IoT Technology platform

Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

System program manager - Wearable & IoT products

Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Manager - Standard cell

Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Program Manager - Design System

Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Library Interface for IO solutions

Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Senior Design Engineer

Wed Aug 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Accelerated leadership Trainee - International Graduate Program

Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Infineon Technologies

Circuit Design Engineer

Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

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