
Pratikkumar Shah
Job Description: To have PPA optimisation : - Expertise on post route timing closure (STA Signoff). Done multiple tape outs,... | Penang, Penang, Malaysia
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Pratikkumar Shah’s Emails pr****@in****.com
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Pratikkumar Shah’s Location Penang, Penang, Malaysia
Pratikkumar Shah’s Expertise Job Description: To have PPA optimisation : - Expertise on post route timing closure (STA Signoff). Done multiple tape outs, includes full chip timing closure, Hyper-scale model, Leakage Power Recovery, Area recovery, MMMC (Multi Modes Multi Corners) ECO Flow - PTECO and Tweaker ECOs - Understanding on ETM, HyperScale Context , HyperScale Models for hire timing analysis - Fishtail netlist clock verification - Hands-on experience of working on technology nodes such as 6nm, 10nm, 14nm, 28nm, 40nm, 55nm - Hands-on experience in Synthesis of complex SoCs at block / subsystem level and refining timing constraints for complex designs with multiple clocks - Good knowledge of EDA tools across Genus (RC) - Fusion Compiler, Tempus (ETS) - PrimeTime (PT), Tweaker - Good knowledge of VLSI process and device characteristics - Closely working with PD implementation team - Good understanding of deep submicron parasitic effects, crosstalk effects, noise etc. - TCL, awk, Perl scripting
Pratikkumar Shah’s Current Industry Intel
Pratikkumar
Shah’s Prior Industry
Intel
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Daiict
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Open Silicon
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Altran
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Work Experience

Intel
Physical Design Timing Engineer
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Altran
Sr. Engineer (Sta)
Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Altran
Sr.Engineer (Sta)
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Open Silicon
Sr. Asic Design Engineer - Ii
Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Open Silicon
Sr. Asic Design Engineer-I
Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Open Silicon
Asic Design Engineer-Ii
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Daiict
Teaching Assistant
Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Structural Design Engineer
— Present