
Rahul Agarwal
● Packaging architect with proven track record of bringing complex packaging platforms from concept phase to High Volume Manufacturing.... | 555 East Washington AvenueApartment 1006, Sunnyvale, United States
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Rahul Agarwal’s Emails ra****@gl****.com
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Rahul Agarwal’s Location 555 East Washington AvenueApartment 1006, Sunnyvale, United States
Rahul Agarwal’s Expertise ● Packaging architect with proven track record of bringing complex packaging platforms from concept phase to High Volume Manufacturing. ● Lead the team who developed industries 1st hybrid bonded 3D stacked devices in HPC (3D V-Cache). ● Evangelized and developed Elevated Fanout Bridge (EFB) technology with multiple OSATs. ● Proven track record in working with various stake holders (both internal and external) to bring novel packaging platforms to the market. ● Proficient in microelectronics packaging with Through Silicon Via (TSV), Hybrid bonding, 3D V-Cache, flip-chip and wire bonding technologies. Expertise in various packaging techniques (anodic, fusion, eutectic, thermo-compression, epoxy, solder, TLP, hybrid bonding), wire bonding, flip chip bonding, soldering, bumping, underfilling, 3D WLP, UTCS, 3D SiC ● Superior knowledge in wafer thinning and handling technology with temporary bonding/thinning/debonding and 3D die to die and die to wafer stacking technology ● Experienced in defining stacking/packaging flows for wide range of projects (3D IC, 3D WLP, chip embedding, MEMS) ● Emphasize on Zero-Level / Wafer-Level packaging based on polymer / metal bonding ● Expertise in process stabilization and improvement through feedback from customers. Risk assessment, specifications and planning definition in close interaction with client ● Technical analysis and benchmarking ● Experienced process integration engineer working on various platforms ● Excellent project management skill and experienced in leading project/teams Specialties: 3D packaging, Stacking, TSV, Hybrid bonding, 3D V-Cache, microbumping, MEMS, Process development and integration,
Rahul Agarwal’s Current Industry Microsoft
Rahul
Agarwal’s Prior Industry
University Of South Florida
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Imec
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Institute Of Microelectronics
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Globalfoundries
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Amd
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Microsoft
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Work Experience

Microsoft
Principal Engineer
Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amd
Principal Member Of Technical Staff
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Senior Member Of Technical Staff
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Member of Technical Staff
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Principal Engineer
Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Institute Of Microelectronics
Scientist
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Institute Of Microelectronics
Senior Research Engineer
Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Imec
Researcher in 3D Packaging
Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of South Florida
Research Assistant
Sat Dec 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)