
Raj Rajasekharan
Package technologist. Package development, Technology analysis, failure analysis. Experience in IP review and technology legal support. Done technology... | Cupertino, California, United States
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Raj Rajasekharan’s Emails ra****@in****.com
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Raj Rajasekharan’s Location Cupertino, California, United States
Raj Rajasekharan’s Expertise Package technologist. Package development, Technology analysis, failure analysis. Experience in IP review and technology legal support. Done technology roadmap. Development of FCBGA, stacked, PoP, WLP, QFN, FD, 3D and Wire Bond packages and MCM & silicon photonics. Experienced in cost reduction activities & yield improvement and streamlining assembly processes. Co-developed and established board level package reliability methods for laptop computers. Experienced in FMEA, DOE and other failure analysis techniques. Management skills including conflict resolution and problem solving skills to move projects and programs. OSAT management and customer relations. Specialties: Package development, Integration, qualification, package reliability. Market analysis and IP evaluation of Package Technologies such as FCBGA, Stacked packages. Development of 2.5D and MCM technology for silicon photonics. Package cost reduction activities and Pb free packaging and copper wire bonding. Additional skills: Customer management, program management and as an interface for Technology transfer.
Raj Rajasekharan’s Current Industry Poet Technologies
Raj
Rajasekharan’s Prior Industry
Bowling Green State University
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Digital Equipment
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Altera
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Intel
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Amkor Technology
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Tessera Technology
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Photonic
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Poet Technologies
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Work Experience

Poet Technologies
Packaging Engineer
Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Photonic
Senior Engineer
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Tessera Technology
Senior Manager, Package Technology Analysis & Development
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Amkor Technology
Sr. Manager, Technical Programs
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Package Engg Manager
Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Package Engg Manager/Sr MTS
Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Digital Equipment
Principal Engineer
Thu Jan 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)
Bowling Green State University
Post Doctoral fellow
Sun Jun 01 1986 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time)