
Rajat Goyal
- Advanced Silicon Packaging Process, Design and Architecture Engineer - 2D, 2.5D and 3D Package Development - Industry leading... | San Jose, California, United States
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Rajat Goyal’s Emails ra****@in****.com
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Rajat Goyal’s Location San Jose, California, United States
Rajat Goyal’s Expertise - Advanced Silicon Packaging Process, Design and Architecture Engineer - 2D, 2.5D and 3D Package Development - Industry leading expertise in DFx - Cost, Manufacturing, Yield and Performance - R&D to HVM on wide spectrum of semiconductor packaging - 12 Yrs of experience on PCB, SLP, HDI, Substrates and Rigid-flexes - Strategic Sourcing and Geo-diversification Specialties: Advanced Semiconductor Packaging R&D, NPI and HVM Supplier Qualification Process Engineering Packaging Design System-in-Package (SiP), Flip-chip & Advanced IC Substrate Technologies
Rajat Goyal’s Current Industry Apple
Rajat
Goyal’s Prior Industry
Fraunhofer Iisb
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Itc
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Purdue University
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Intel
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Apple
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Work Experience

Apple
Substrate Packaging Engineer
Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Engineering Manager - Package Mechanicals and Design Rules
Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Rule Owner - ATTD Design
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Process Engineer
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Purdue University
Graduate Research Assistant
Sun Aug 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Itc
Asst. Engineer - Projects
Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Itc
Assistant (Under Training)
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Fraunhofer Iisb
Summer Research Intern
Tue May 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)