Rajat Sengupta
Senior SOC designer with 13 years of experience in Multi Voltage Physical Design, SubSystem and Full Chip level... | Portland, Oregon, United States
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Rajat Sengupta’s Emails ra****@in****.com
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Rajat Sengupta’s Location Portland, Oregon, United States
Rajat Sengupta’s Expertise Senior SOC designer with 13 years of experience in Multi Voltage Physical Design, SubSystem and Full Chip level timing (STA) convergence on sub 5nm high performance designs including signoff for tapeout. Lead partition and timing convergence for subsystems over multiple projects.
Rajat Sengupta’s Current Industry Apple
Rajat
Sengupta’s Prior Industry
Stmicroelectronics
|
Connection One Research Lab
|
Intel
|
Apple
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Work Experience
Apple
Senior Physical Design and STA Engineer
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Full Chip Timing Owner
Sat Mar 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior SOC Design Engineer/ Mentor
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
CPU Design Engineer
Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
R&D Intern, Memory I/O Circuits group
Fri Aug 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Connection One Research Lab
Graduate Research Assistant
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Intern, Front End Technology CMOS Memories group
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Rajat Sengupta Email Addresses
FAQ About Rajat Sengupta
-
Rajat Sengupta is located at
Portland, Oregon, United States -
Rajat Sengupta is a
Senior SOC designer with 13 years of experience in Multi Voltage Physical Design, SubSystem and Full Chip level timing (STA) convergence on sub 5nm high performance designs including signoff for tapeout. Lead partition and timing convergence for subsystems over multiple projects. Apple -
Rajat Sengupta currently works in the
Apple -
Rajat Sengupta specializes in
Senior SOC designer with 13 years of experience in Multi Voltage Physical Design, SubSystem and Full Chip level timing (STA) convergence on sub 5nm high performance designs including signoff for tapeout. Lead partition and timing convergence for subsystems over multiple projects. -
Rajat Sengupta speaks the following languages:
No languages available. -
Rajat Sengupta has prior experience in the following industries:
Intel , Intel , Intel , Intel , Connection One Research Lab , Stmicroelectronics -
Rajat Sengupta has the following professional experience:
Apple , Intel , Intel , Intel , Intel , Connection One Research Lab , Stmicroelectronics . -
You can view Rajat Sengupta’s
LinkedIn profile at LinkedIn URL. -
Rajat Sengupta’s work email addresses are
[email protected] . -
Rajat Sengupta works at
Apple
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