
Rajesh Chopra
Over 20+ years of experience in different aspects of Chip Design including Architecture, Micro-architecture, RTL, Verification, Chip Integration,... | San Ramon, California, United States
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Rajesh Chopra’s Emails rc****@fu****.com
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Social Media
Rajesh Chopra’s Location San Ramon, California, United States
Rajesh Chopra’s Expertise Over 20+ years of experience in different aspects of Chip Design including Architecture, Micro-architecture, RTL, Verification, Chip Integration, Synthesis, Timing, P&R, Emulation (Palladium & Protium) and FPGA (Altera & Xilinx) verification. Designed Chips at 90nm, 65nm, 45nm, 32nm and 22nm (SOI and Bulk) 18 Issued Patents (US9699079, US6629207, US6598128, US6591340, US6553460, US6412043, US6434665, US6496905, US7587643, US8069385, US8954803, JP2001202287, JP201147857, JP2001142780, JP2001142779, JP2001147854, TW508493, TW505862)
Rajesh Chopra’s Current Industry Microsoft
Rajesh
Chopra’s Prior Industry
Hitachi Microsystems
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Pmc Sierra
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T Ram
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Mosys
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Netspeed Systems
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Stealth Startup
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Fungible Inc Acquired By Microsoft
|
Microsoft
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Work Experience

Microsoft
Senior Director of Silicon Engineering @ Microsoft Azure
Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Fungible Inc Acquired By Microsoft
Senior Director of Emulation & Prototyping
Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Stealth Startup
Director Of Engineering
Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Netspeed Systems
Sr. Principal Engineer
Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Mosys
Principal Design Engineer
Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
T Ram
Director of Engineering
Sat Jun 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Pmc Sierra
Sr. Staff Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Hitachi Microsystems
Staff design Engineer
Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)