
Raju Hp
Experience Summary :: ================= DFT Architecture: =================> Scan insertion , scan compression, DRC analysis , low coverage analysis and ... | Mandya, Mandya, India
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Raju Hp’s Emails ra****@in****.com
Raju Hp’s Phone Numbers 1858651****
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Raju Hp’s Location Mandya, Mandya, India
Raju Hp’s Expertise Experience Summary :: ================= DFT Architecture: =================> Scan insertion , scan compression, DRC analysis , low coverage analysis and pattern generation and simulation . MBIST Design : =================> implementation , synthesis and verification JTAG : =================> Implementing test cases for mandatory and other test mode IR verification and simulation. Flash memory testing =================> Involve implementation of custom flash memory testing through JTAG port of SoC with SPI interface. Specialties: SoC DFT implementation, MBIST design, Flash memory testing, JTAG, verilog, perl, SED, AWK, Unix c-sehll scripting. Having experience on these TOOL 's ================================= Simulation : ModelSim, NC-sim Synthesis : Design Compiler Scan Insertion : DFT-MAX, ATPG : TestKompress, Encounter Test Formal Verification : LEC Scripting : Perl, Cshell , SED , AWK, and GREP . Academics summary ========================= I Completed Master degree in Embedded and Wireless Technology from Manipal University. Completed one year internship at STMicroelectronics. Internship Details : --------------------------- Project Title : " To implement STIL based simulations of BOUNDARY SCAN for DFT Environment " Role : • Responsible for BSD STIL patterns’ implementation & simulation, stuck at ault and transition fault ATPG STIL patterns’ simulation, OCC active STIL patterns’ simulation and sending to TE for an SoC for Leading Gaming console provider. • Additionally writing Perl script and Cshell script to generate test cases and to automate some part of the work.
Raju Hp’s Current Industry Intel
Raju
Hp’s Prior Industry
Stmicroelectronics
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Qualcomm
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Intel
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Work Experience

Intel
Soc Design Engineer
Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Dft Consultent
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Stmicroelectronics
Dft Intern
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)