Raju Ponnaganti

Raju Ponnaganti

Professional Exposure: Experience in FPGA based RTL implementation using Verilog/VHDL/System Verilog. SoC design and integration. Experience in digital front end design... | Chennai, Chennai, India

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Work Experience

Hcl Technologies

Technical Lead

Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Moschip

Sr. Design Engineer

Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Astra Microwave Products

Design Engineer

Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Rci

Design Engineer

Mon Aug 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Hcl Enterprise

Technical Lead

— Present

Skills

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