Rambir Singh
Architect for PDK/iPDK development – • Technology Files : virtuoso,custom-compiler,ADS,klayout,Helic RaptorX • PCells/PyCells : PAS, STeP, PcellDesigner, Pycellstudio • Symbols, CDF, callbacks-TCL/SKILL, Netlist • Simulation –... | Arnhem, Gelderland, Netherlands
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Rambir Singh’s Emails ra****@nx****.com
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Rambir Singh’s Location Arnhem, Gelderland, Netherlands
Rambir Singh’s Expertise Architect for PDK/iPDK development – • Technology Files : virtuoso,custom-compiler,ADS,klayout,Helic RaptorX • PCells/PyCells : PAS, STeP, PcellDesigner, Pycellstudio • Symbols, CDF, callbacks-TCL/SKILL, Netlist • Simulation – Spectre, ADS, HSPICE • DRC-LVS for PVS, ICV, Klayout, ADS • Liaison with Technology teams – PDK team Architect for Mask Data Prep – • Reticle/Mask layout floor plan • Handling test structures PCM/OCM/mask identification, barcodes etc • Layer operations, Booleans, sizing etc • Tapeout to Mask-house, FAB • Liaison with Design Teams-Mask house-FAB Automation/Design Flow development • Build flow for PDK, iPDK, Tapeout etc. • Automation scripting with Virtuoso, Custom Compiler, Keysight-ADS, Klayout • Automation for PDK QA, DRC QualCells, MDP flow-Xyalis tools • Integration of EDA tools within each other • Development of EM stack for Keysight Momentum, Helic RaptorX • Benchmark EDA tools and Introduce to the design teams • Liaison with EDA vendors – Design Teams Cadence-SKILL,Ocean,Bash,Ruby,Python,TCL/Keysight-AEL,Shell/Bash
Rambir Singh’s Current Industry Cadence Design Systems
Rambir
Singh’s Prior Industry
Synopsys
|
Cadence Design Systems
|
Nxp Semiconductors
|
Ampleon
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Work Experience
Cadence Design Systems
Product Engineering Architect
Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Ampleon
Director(EDA, ChipFinishing, Mask Data Preparation)
Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Ampleon
PDK-Design Flow-Mask Layout Architect
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
CAD Engineer
Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Lead Engineer(PDK Services)
Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
PDK Developer
Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Rambir Singh Email Addresses
FAQ About Rambir Singh
-
Rambir Singh is located at
Arnhem, Gelderland, Netherlands -
Rambir Singh is a
Architect for PDK/iPDK development – • Technology Files : virtuoso,custom-compiler,ADS,klayout,Helic RaptorX • PCells/PyCells : PAS, STeP, PcellDesigner, Pycellstudio • Symbols, CDF, callbacks-TCL/SKILL, Netlist • Simulation – Spectre, ADS, HSPICE • DRC-LVS for PVS, ICV, Klayout, ADS • Liaison with Technology teams – PDK team Architect for Mask Data Prep – • Reticle/Mask layout floor plan • Handling test structures PCM/OCM/mask identification, barcodes etc • Layer operations, Booleans, sizing etc • Tapeout to Mask-house, FAB • Liaison with Design Teams-Mask house-FAB Automation/Design Flow development • Build flow for PDK, iPDK, Tapeout etc. • Automation scripting with Virtuoso, Custom Compiler, Keysight-ADS, Klayout • Automation for PDK QA, DRC QualCells, MDP flow-Xyalis tools • Integration of EDA tools within each other • Development of EM stack for Keysight Momentum, Helic RaptorX • Benchmark EDA tools and Introduce to the design teams • Liaison with EDA vendors – Design Teams Cadence-SKILL,Ocean,Bash,Ruby,Python,TCL/Keysight-AEL,Shell/Bash Cadence Design Systems -
Rambir Singh currently works in the
Cadence Design Systems -
Rambir Singh specializes in
Architect for PDK/iPDK development – • Technology Files : virtuoso,custom-compiler,ADS,klayout,Helic RaptorX • PCells/PyCells : PAS, STeP, PcellDesigner, Pycellstudio • Symbols, CDF, callbacks-TCL/SKILL, Netlist • Simulation – Spectre, ADS, HSPICE • DRC-LVS for PVS, ICV, Klayout, ADS • Liaison with Technology teams – PDK team Architect for Mask Data Prep – • Reticle/Mask layout floor plan • Handling test structures PCM/OCM/mask identification, barcodes etc • Layer operations, Booleans, sizing etc • Tapeout to Mask-house, FAB • Liaison with Design Teams-Mask house-FAB Automation/Design Flow development • Build flow for PDK, iPDK, Tapeout etc. • Automation scripting with Virtuoso, Custom Compiler, Keysight-ADS, Klayout • Automation for PDK QA, DRC QualCells, MDP flow-Xyalis tools • Integration of EDA tools within each other • Development of EM stack for Keysight Momentum, Helic RaptorX • Benchmark EDA tools and Introduce to the design teams • Liaison with EDA vendors – Design Teams Cadence-SKILL,Ocean,Bash,Ruby,Python,TCL/Keysight-AEL,Shell/Bash -
Rambir Singh speaks the following languages:
No languages available. -
Rambir Singh has prior experience in the following industries:
Ampleon , Ampleon , Nxp Semiconductors , Cadence Design Systems , Synopsys -
Rambir Singh has the following professional experience:
Cadence Design Systems , Ampleon , Ampleon , Nxp Semiconductors , Cadence Design Systems , Synopsys . -
You can view Rambir Singh’s
LinkedIn profile at LinkedIn URL. -
Rambir Singh’s work email addresses are
[email protected] . -
Rambir Singh works at
Cadence Design Systems
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