
Richard Todd
I.C. Mask Designer with over 30 years of experience doing cell, block and chip level floorplanning, layout and... | Minneapolis, Minnesota, United States
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Richard Todd’s Emails rt****@mi****.com
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Richard Todd’s Location Minneapolis, Minnesota, United States
Richard Todd’s Expertise I.C. Mask Designer with over 30 years of experience doing cell, block and chip level floorplanning, layout and verification in IBM 32SOI and TSMC 90, 40 & 28nm processes. Briefly worked with TSMC 12/16nm finfet process and currently working with 5nm. Specialties: Layout and verification of high-speed custom analog circuits and CMOS SerDes, PLL, high speed I/O and ESD devices using Cadence Virtuoso, Cadence PVS/Pegasus verification tools. Also have previous experience with Mentor Calibre & Assura. Support chip-level layout of complex system- level designs to provide customers with chips that meet performance requirements. Provide guidance to contractors and engineers in regard to layout-specific rules and guidelines across multiple processes. Work with other design centers across the country and globe on projects, ensuring effective collaboration.
Richard Todd’s Current Industry Micron Technology
Richard
Todd’s Prior Industry
Unisys Defense Systems
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Vtc
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Amcc
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Toshiba America Electronic Components
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Micron Technology
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Work Experience

Micron Technology
Senior Mask Designer
Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Toshiba America Electronic Components
Physical Design Specialist
Tue Oct 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Amcc
Senior Lead Mask Designer
Fri Oct 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Vtc
Senior I.C. Mask Designer
Fri Oct 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Vtc
Equipment Maintenance Technician
Mon Jan 01 1990 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)
Unisys Defense Systems
Engineering Assistant
Tue Jan 01 1985 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time)