
Saad Zahid
Accomplished Verification Engineer with experience in Interconnects, NoC, Caches (L1 & L2), Cache Coherency, SSD Controller, Multi-Core Network... | Austin, Texas, United States
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Saad Zahid’s Emails sa****@hg****.com
Saad Zahid’s Phone Numbers No phone number available.
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Saad Zahid’s Location Austin, Texas, United States
Saad Zahid’s Expertise Accomplished Verification Engineer with experience in Interconnects, NoC, Caches (L1 & L2), Cache Coherency, SSD Controller, Multi-Core Network Processors and networking industries and proven track record of 7+ successful multi-million gate SoC / ASICs from concept to silicon. Excellent interpersonal and project management skills complemented by strong technical and problem solving capabilities. > Achieved functional verification closure on 9+ SoC/FPGA/ASIC by architecting and developing self-checking verification environments using System-Verilog, UVM methodologies, C++ / C, PLI, Shell & Perl Scripting. > Mastery of achieving 100% coverage by writing targeted-random, directed and corner cases on un-exercised RTL logics and boundary conditions as well as discretely random nightly regressions suites. Specialties: Interconnects verification, NoC, SystemC AT modeling, Multi-Core SoC / Caches (L1 & L2) / Cache Coherency / Performance Verification / SSD Controller / Network Processor / Traffic Manager / Test Plan / UVM / Self Checking Test bench / Constraint Random Stimulus / C & C++ Reference Model (cycle-accurate & transaction-accurate) / Scoreboard Development / Coverage Analysis / Regression / Exhaustive & Corner Cases / System-Verilog / PLI
Saad Zahid’s Current Industry Arteris Ip
Saad
Zahid’s Prior Industry
Conexant
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Axiom Design Automation
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Tellabs
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Netronome Systems
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Huawei
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Hgst A Western Digital
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Oracle Labs
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Arteris Ip
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Work Experience

Arteris Ip
Director of Engineering
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Oracle Labs
Consulting Member of Technical Staff
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Hgst A Western Digital
Sr. Principal Verification Engineer / Verification Architect + Lead
Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Huawei
Verification Lead
Thu Oct 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Netronome Systems
Senior Member of Technical Staff
Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Sep 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Tellabs
SENIOR VERIFICATION ENGINEER
Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Axiom Design Automation
SENIOR CORPORATE APPLICATION ENGINEER
Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Conexant
STAFF VERIFICATION ENGINEER
Mon Jun 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)