
Sandeep L
With over 20 years of work experience in the semiconductor industry, I am a Principal Technology Programs Manager... | Folsom, California, United States
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Sandeep L’s Emails sa****@in****.com
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Sandeep L’s Location Folsom, California, United States
Sandeep L’s Expertise With over 20 years of work experience in the semiconductor industry, I am a Principal Technology Programs Manager at Intel Corporation, where I lead the product enabling that encompasses design, strategy, partner development, and delivery of cutting-edge semiconductor design IP and SoC solutions for client, automotive, data center, AI, IoT and networking markets and applications. I have a strong background in GPU and CPU design, as well as system verification, which enables me to manage complex projects and teams across multiple domains and geographies. I also have a Master of Business Administration and a Master of Science in Electrical and Electronics Engineering, which equip me with the skills and knowledge to align the technology vision and roadmap with the business strategy and goals. As a Technology Investment Strategist at Intel Capital, I leveraged my technical and market insights to identify and evaluate emerging opportunities and trends in the semiconductor space, and supported the portfolio companies with strategic guidance and mentorship. I am passionate about driving innovation and excellence in the semiconductor industry, and I value collaboration, diversity, and learning as the key drivers of success. I enjoy working with the team that shares my vision and values, and that challenges me to grow and contribute to the advancement of technology and society.
Sandeep L’s Current Industry Intel
Sandeep
L’s Prior Industry
Intel
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Work Experience

Intel
Principal Strategic Technology Programs Lead
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Principal Technical Program Manager, Semiconductor Design IP and SoC
Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Sr. Technical Sourcing Engineer, Design IP Technology Strategic Planning
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Platform Architect, CPU and Graphics System Validation
Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Graphics Hardware Design Engineer, Visual Technologies Team
Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Product Development Engineer, Chipset and Graphics
Tue Mar 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Analong Design Engineer
Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)