
Sandip Das
- 22+ years of industry experience spanning diverse areas of Computer Architecture, Network on Chip/Interconnects, Deep Neural Networks, Wireless... | 151 Alice B Toklas PlaceUnit 403, San Francisco, United States
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Sandip Das’s Emails sa****@ca****.technology
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Sandip Das’s Location 151 Alice B Toklas PlaceUnit 403, San Francisco, United States
Sandip Das’s Expertise - 22+ years of industry experience spanning diverse areas of Computer Architecture, Network on Chip/Interconnects, Deep Neural Networks, Wireless and Networking, Coherency, Memory sub-system, High Speed IO (Ethernet, PCIe, CXL, UCIe), SOCs, Automotive ADAS and Infotainment. - Working experience in Scalable silicon Architecture for L2++, L3 and L4 ADAS and understanding/analyzing work loads for AD functions and pipeline. - Working experience on SOC for Automotive Infotainment. - Experience and understanding of AD and Infotainment ECUs - Experience and knowledge in Neural Processing Engine Architectures involving MAC Arrays, TCMs, Intelligent DMAs, Vector Engines with understanding of CNN, Transformers and LLMs networks. - Architecture and design experience in 5G wireless baseband solutions for L2/L3 layers : Accelerators, compute tiles, HW/SW co-working and SoC Architecture - ARM processor and sub-systems architecture and design experience - Design experiences with AXI, AMBA and OCP Bus protocols - PCIe sub-system architecture and design experience - Experience in Sparc Microprocessor design (CMP/SMT) at Sun Microsystems/Oracle - Computer Vision involving CNN, YOLO, Vision Transformers Specialties: multi-core, multi-threaded, high throughput microprocessor architecture, NoC, Coherency, Heterogeneous SoC, Automotive, PCIe architecture and protocol, FPGA, Non volatile memories, Peripherals (I2C, xSPI Octa, GPIO ) ARM architecture, AXI/AMBA protocol, Micro-architecture definition, logic design and RTL coding, verification, ASIC and custom design flows, circuit design
Sandip Das’s Current Industry Cariad
Sandip
Das’s Prior Industry
Alliance Semiconductor
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Sun Microsystem
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Oracle
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Broadcom
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Netspeed Systems
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Intel
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Luminous Computing
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Aeva
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Cariad
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Work Experience

Cariad
Senior Principal SoC Architect
Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Aeva
SoC Architect
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Luminous Computing
Principal Engineer
Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
RTL/HW Design Engineer at Intel
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Netspeed Systems
Principal Engineer
Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Senior Staff Engineer (RTL/front-end)
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Oracle
Hardware Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Oracle
Hardware engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Sun Microsystem
Hardware engineer
Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Alliance Semiconductor
Design Engineer
Tue Jun 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)