
Sanjeev Kumar
• Worked on verification of Server Processor, SSD flash controller, storage chips, TCP offload engine, Analog Devices processors and... | Mountain View, California, United States
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Sanjeev Kumar’s Emails sa****@ro****.com
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Sanjeev Kumar’s Location Mountain View, California, United States
Sanjeev Kumar’s Expertise • Worked on verification of Server Processor, SSD flash controller, storage chips, TCP offload engine, Analog Devices processors and ARM based SoCs. • Fabric/multi-processor coherency verification - MOSI/MOSI+ • Expert in UVM/VMM/SV/C/C++ based verification. • Expert in power aware verification. • Performed development of golden models C/C++, Systemverilog and Verilog • Functional Coverage models and Code Coverage analysis • Developed Systemverilog Assertions • Excellent debugging skills • Performed block level and system level verification • Performed RTL Coding and equivalency check • Expert in script development • Verification infrastructure development, tool developments etc. • Linting checks using Insure++ and Purify • Developed License Model • Post silicon Validation • Emulation using Palladium
Sanjeev Kumar’s Current Industry Rivos
Sanjeev
Kumar’s Prior Industry
Bharat Electronics
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Analog Devices
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Emulex Communications
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Link Logik
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Smartplay Technologies
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Amd
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Qualcomm Systems
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Rockwell Collins
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Micron
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Microsoft
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Marvell Semiconductor
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Rivos
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Work Experience

Rivos
Principal Member of Technical Staff
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Marvell Semiconductor
Principal Engineer, Design Verification
Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Microsoft
Verification
Sun Nov 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Micron
Verification Consultant
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Rockwell Collins
Verification Engineer - Consultant
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm Systems
Engineer-3
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies
Lead Engineer
Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Verification Infrastructure
Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Emulex Communications
Senior Engineer
Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Emulex Communications
Senior Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Link Logik
Lead Design Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Analog Devices
Engineer
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Bharat Electronics
Trainee
Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)