Sathappan Palaniappan
Sathappan Palaniappan is a Principal Engineer at Broadcom. He's an expert in IP development and AI chip emulation... | San Francisco Bay Area, San Francisco Bay Area, United States
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Sathappan Palaniappan’s Emails sp****@br****.com
Sathappan Palaniappan’s Phone Numbers No phone number available.
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Sathappan Palaniappan’s Location San Francisco Bay Area, San Francisco Bay Area, United States
Sathappan Palaniappan’s Expertise Sathappan Palaniappan is a Principal Engineer at Broadcom. He's an expert in IP development and AI chip emulation model creation, having innovated emulation models directly from gate-level netlists for major platforms and clients like Google and Ericson. He led the design for Cisco's Enterprise Router, Broadcom’s first 16nm design. His work includes leading SSD ARM Sub-System Designs, resulting in several patents. Palaniappan holds 5 patents, with notable contributions in embedded memory power management and asynchronous memory access. He is a senior member of IEEE and serves on the Technical Committee of DAC (Design Automation Conference) and SNUG Silicon Valley (Synopsys Global Users Community). His publications and peer reviews further highlight his expertise. He holds a Masters degree in VLSI Designs and additional degrees in electronics and Applied Sciences.
Sathappan Palaniappan’s Current Industry Broadcom
Sathappan
Palaniappan’s Prior Industry
Salzer Electronics
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Hcl Infosystems
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Thiagarajar College Of Engineering
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Jasmin Infotech
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Mindtree
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Conexant
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Broadcom
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Work Experience
Broadcom
Principal Engineer
Sat Dec 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Conexant
Senior Design Engineer
Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Mindtree
Staff Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Jasmin Infotech
Dsp Engineer
Wed Oct 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Thiagarajar College Of Engineering
Lecturer
Sat Mar 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Hcl Infosystems
Engineer
Sun Sep 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Salzer Electronics
Engineer
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Sathappan Palaniappan Email Addresses
FAQ About Sathappan Palaniappan
-
Sathappan Palaniappan is located at
San Francisco Bay Area, San Francisco Bay Area, United States -
Sathappan Palaniappan is a
Sathappan Palaniappan is a Principal Engineer at Broadcom. He's an expert in IP development and AI chip emulation model creation, having innovated emulation models directly from gate-level netlists for major platforms and clients like Google and Ericson. He led the design for Cisco's Enterprise Router, Broadcom’s first 16nm design. His work includes leading SSD ARM Sub-System Designs, resulting in several patents. Palaniappan holds 5 patents, with notable contributions in embedded memory power management and asynchronous memory access. He is a senior member of IEEE and serves on the Technical Committee of DAC (Design Automation Conference) and SNUG Silicon Valley (Synopsys Global Users Community). His publications and peer reviews further highlight his expertise. He holds a Masters degree in VLSI Designs and additional degrees in electronics and Applied Sciences. Broadcom -
Sathappan Palaniappan currently works in the
Broadcom -
Sathappan Palaniappan specializes in
Sathappan Palaniappan is a Principal Engineer at Broadcom. He's an expert in IP development and AI chip emulation model creation, having innovated emulation models directly from gate-level netlists for major platforms and clients like Google and Ericson. He led the design for Cisco's Enterprise Router, Broadcom’s first 16nm design. His work includes leading SSD ARM Sub-System Designs, resulting in several patents. Palaniappan holds 5 patents, with notable contributions in embedded memory power management and asynchronous memory access. He is a senior member of IEEE and serves on the Technical Committee of DAC (Design Automation Conference) and SNUG Silicon Valley (Synopsys Global Users Community). His publications and peer reviews further highlight his expertise. He holds a Masters degree in VLSI Designs and additional degrees in electronics and Applied Sciences. -
Sathappan Palaniappan speaks the following languages:
No languages available. -
Sathappan Palaniappan has prior experience in the following industries:
Conexant , Mindtree , Jasmin Infotech , Thiagarajar College Of Engineering , Hcl Infosystems , Salzer Electronics -
Sathappan Palaniappan has the following professional experience:
Broadcom , Conexant , Mindtree , Jasmin Infotech , Thiagarajar College Of Engineering , Hcl Infosystems , Salzer Electronics . -
You can view Sathappan Palaniappan’s
LinkedIn profile at LinkedIn URL. -
Sathappan Palaniappan’s work email addresses are
[email protected] . -
Sathappan Palaniappan works at
Broadcom
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