Sathish B
1. Totally 11 years of experience in Physical design domain in both block and SOC level PnR ... | Burnaby, Burnaby, Canada
*50 free lookup(s) per month.
No credit card required.
Sathish B’s Emails sa****@mi****.com
Sathish B’s Phone Numbers No phone number available.
Social Media
Sathish B’s Location Burnaby, Burnaby, Canada
Sathish B’s Expertise 1. Totally 11 years of experience in Physical design domain in both block and SOC level PnR implementation. 2. Worked on PCIEGEN4 SOC's from netlist to gdsii , Area is 171.6mm2 , 130M gate count and the maximum frequency is 1GHz 3.Successfully implemented LPDD4 DDR_PHY and Controller as a subsystem from Synthesis to GDSII. There are many challenges such as Constraints development, Hierarchical synthesis, Are optimization, Block size Estimation, Creating IO ring, IO decap calculation, PLL placement, Skew Balancing between the slice's. Slice's to the IO pads 4. Currently leading a Turnkey project from netlist to gdsii. There are many challenges such as Resource allocation and management, Project executions plan, Customer Interaction from the different geographical locations. Die size estimation, Channel estimation etc.. 5. Expertise in Bumps to IO Pads routing(RDL routing). 6. Working knowledge of Advanced Timing concepts like POCV, LOCV, set rail voltage etc. 7. Signal Integrity: Crosstalk, Signal Electromigration 8. Power Integrity: IR-drop , power/ground Electromigration 9. Low Power: Multi-Vt, fine/coarse grained clock gating 10. Timing Analysis: Multi-Corner-Multi-Mode 11. Successfully completed 12 tapeouts till date. 12. Working knowledge of DC-topology. 13. Ability to do multi-task and meet deadlines. TOOLS USED : Synopsys: ICC, ICC-II, STAR-RC, LEC, PRIME TIME, DC Compiler, ICV, Dorado Cadence: INNOVUS, QRC, Voltus, PVS, Pegasus Mentor: Calibre ATopTech : Aprisa
Sathish B’s Current Industry Microchip Technology
Sathish
B’s Prior Industry
Pmc Sierra
|
Smartplay Technologies
|
Consultant At Broadcom From Tech Vulcan
|
Synopsys
|
Microsemi
|
Eximius Design
|
Microchip Technology
Not the Sathish B you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience
Microchip Technology
Principal Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Eximius Design
Physical Design Technical Lead
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Microsemi
Principal Physical design Engineer-SOC lead
Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
ASIC PHYSICAL DESIGN ENGINEER-II
Sat Mar 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Consultant At Broadcom From Tech Vulcan
Physical Design Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies
Physical design Engineer.
Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Pmc Sierra
PD engineer
Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Sathish B Email Addresses
FAQ About Sathish B
-
Sathish B is located at
Burnaby, Burnaby, Canada -
Sathish B is a
1. Totally 11 years of experience in Physical design domain in both block and SOC level PnR implementation. 2. Worked on PCIEGEN4 SOC's from netlist to gdsii , Area is 171.6mm2 , 130M gate count and the maximum frequency is 1GHz 3.Successfully implemented LPDD4 DDR_PHY and Controller as a subsystem from Synthesis to GDSII. There are many challenges such as Constraints development, Hierarchical synthesis, Are optimization, Block size Estimation, Creating IO ring, IO decap calculation, PLL placement, Skew Balancing between the slice's. Slice's to the IO pads 4. Currently leading a Turnkey project from netlist to gdsii. There are many challenges such as Resource allocation and management, Project executions plan, Customer Interaction from the different geographical locations. Die size estimation, Channel estimation etc.. 5. Expertise in Bumps to IO Pads routing(RDL routing). 6. Working knowledge of Advanced Timing concepts like POCV, LOCV, set rail voltage etc. 7. Signal Integrity: Crosstalk, Signal Electromigration 8. Power Integrity: IR-drop , power/ground Electromigration 9. Low Power: Multi-Vt, fine/coarse grained clock gating 10. Timing Analysis: Multi-Corner-Multi-Mode 11. Successfully completed 12 tapeouts till date. 12. Working knowledge of DC-topology. 13. Ability to do multi-task and meet deadlines. TOOLS USED : Synopsys: ICC, ICC-II, STAR-RC, LEC, PRIME TIME, DC Compiler, ICV, Dorado Cadence: INNOVUS, QRC, Voltus, PVS, Pegasus Mentor: Calibre ATopTech : Aprisa Microchip Technology -
Sathish B currently works in the
Microchip Technology -
Sathish B specializes in
1. Totally 11 years of experience in Physical design domain in both block and SOC level PnR implementation. 2. Worked on PCIEGEN4 SOC's from netlist to gdsii , Area is 171.6mm2 , 130M gate count and the maximum frequency is 1GHz 3.Successfully implemented LPDD4 DDR_PHY and Controller as a subsystem from Synthesis to GDSII. There are many challenges such as Constraints development, Hierarchical synthesis, Are optimization, Block size Estimation, Creating IO ring, IO decap calculation, PLL placement, Skew Balancing between the slice's. Slice's to the IO pads 4. Currently leading a Turnkey project from netlist to gdsii. There are many challenges such as Resource allocation and management, Project executions plan, Customer Interaction from the different geographical locations. Die size estimation, Channel estimation etc.. 5. Expertise in Bumps to IO Pads routing(RDL routing). 6. Working knowledge of Advanced Timing concepts like POCV, LOCV, set rail voltage etc. 7. Signal Integrity: Crosstalk, Signal Electromigration 8. Power Integrity: IR-drop , power/ground Electromigration 9. Low Power: Multi-Vt, fine/coarse grained clock gating 10. Timing Analysis: Multi-Corner-Multi-Mode 11. Successfully completed 12 tapeouts till date. 12. Working knowledge of DC-topology. 13. Ability to do multi-task and meet deadlines. TOOLS USED : Synopsys: ICC, ICC-II, STAR-RC, LEC, PRIME TIME, DC Compiler, ICV, Dorado Cadence: INNOVUS, QRC, Voltus, PVS, Pegasus Mentor: Calibre ATopTech : Aprisa -
Sathish B speaks the following languages:
No languages available. -
Sathish B has prior experience in the following industries:
Eximius Design , Microsemi , Synopsys , Consultant At Broadcom From Tech Vulcan , Smartplay Technologies , Pmc Sierra -
Sathish B has the following professional experience:
Microchip Technology , Eximius Design , Microsemi , Synopsys , Consultant At Broadcom From Tech Vulcan , Smartplay Technologies , Pmc Sierra . -
You can view Sathish B’s
LinkedIn profile at LinkedIn URL. -
Sathish B’s work email addresses are
[email protected] . -
Sathish B works at
Microchip Technology
People you may be interested in
- Nicole Carvalho
- Luke Cyphers
- Devankumaran Dlkumaran
- Tsvi Stern
- Aleksander Ponichtera
- Stephen Mcroberts
- Adam Winn-clare
- Sharath Hiremat
Accountant | Financial Analyst | Accounts Payable
Regional Sales Director
Worked at Consolidated Contractors International Company
Site Manager
Jestem doradcą klienta, zajmuje się polecaniem produktów z oferty x-kom
transportation at vistar
Student Progress Advisor at University of Newcastle
Technology Consultant at Hewlett Packard Enterprise