
Saurabh Chavan
No headline available | Taiwan
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Saurabh Chavan’s Emails sc****@ts****.com
Saurabh Chavan’s Phone Numbers No phone number available.
Social Media
Saurabh Chavan’s Location Taiwan
Saurabh Chavan’s Expertise Memory and Test-chip Design Engineer at TSMC
Saurabh Chavan’s Current Industry Tsmc
Saurabh
Chavan’s Prior Industry
Mood Indigo Iit Bombay
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Techfest Iit Bombay
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The Entrepreneurship Cell Iit Bombay
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Texas Instruments
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Tsmc
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Work Experience

Tsmc
Digital Designer, Advanced HD Memory Department
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Texas Instruments
Design Verification Engineer, Internship
Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
The Entrepreneurship Cell Iit Bombay
Coordinator,Events
Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
The Entrepreneurship Cell Iit Bombay
Organizer,Corporate Relationships
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Techfest Iit Bombay
Organizer,Media and marketting
Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Mood Indigo Iit Bombay
Organizer
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)