
Saurabh Pandey
I am a certified Project manager in senior role (IPMA Level C) and an experienced engineering R&D professional... | Villach, Carinthia, Austria
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Saurabh Pandey’s Emails sa****@ya****.co
Saurabh Pandey’s Phone Numbers 1408956896044117952****
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Saurabh Pandey’s Location Villach, Carinthia, Austria
Saurabh Pandey’s Expertise I am a certified Project manager in senior role (IPMA Level C) and an experienced engineering R&D professional with deep knowledge in materials science, semiconductor research and manufacturing. I have GaN on Si and Si MOSFET development experience at 6inch and 8inch wafer diameter. I have led projects to bring GaN technology into real products and production friendly to sustain high volume ramp up. I am also actively involved in reliability, qualification and quality related topics to ensure released technologies are not just production friendly but serve the customers at best. I have I also have very relevant experience in area of data analysis, project co-ordination, technical management with industries/research institutes. Specialties: Project Co-ordination and management, Leadership, Foundry experience, Business focus, Wide band gap materials, GaN, MOSFETs, Research and development, , Semiconductor physics, Materials science, Reliability and characterizations, Data analysis,
Saurabh Pandey’s Current Industry Infineon Technologies
Saurabh
Pandey’s Prior Industry
Matcon
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University Of Bologna
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Nxp Semiconductors
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Institute Of Materials Research And Engineering
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Nexperia
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Infineon Technologies
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Work Experience

Infineon Technologies
Senior Project Manager
Sun Jan 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Infineon Technologies
Project Manager
Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Nexperia
Lead Platform Development Engineer
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
Reliability Engineer
Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Institute Of Materials Research And Engineering
Visiting Industry Collaborator
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
Senior Engineer (Research)
Sat Sep 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Bologna
Phd, Marie Curie Research Fellow
Tue Sep 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Matcon
Research Intern
Mon Dec 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)