
Shailesh Patel
Proven and adaptable Release Engineering experience in dynamic environments with strong analytic proficiency. Talented cloud reliability engineer with... | Arlington, Massachusetts, United States
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Shailesh Patel’s Emails sh****@fn****.com
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Shailesh Patel’s Location Arlington, Massachusetts, United States
Shailesh Patel’s Expertise Proven and adaptable Release Engineering experience in dynamic environments with strong analytic proficiency. Talented cloud reliability engineer with experience building and deploying software applications on cloud servers using Git, SVN, Maven, JIRA, Clearcase, Clearquest, TeamCity, Jenkins, Bamboo, Sonarqube, Build Forge and Tivoli. Seasoned project manager with experience preparing well documented deployment projects and deliverables for all environments with tight deadlines. Demonstrated technical leadership through mentoring and training team members to maximize productivity. Excellent verbal, interpersonal communication and client management skills. Specialties: Proficient in Jenkins, Maven, Git, SVN, Rational Clearcase/Clearquest, Rational Team Concert, Nexus Repository, JFrog Artifactory, JIRA, Bamboo, TeamCity, CloudBees, Sonarqube, BuildForge, Tivoli.
Shailesh Patel’s Current Industry Fnz
Shailesh
Patel’s Prior Industry
Circuit Fabrication
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State Street
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Mit Lincoln Laboratory
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Work Experience

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Cloud Build Engineer
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mit Lincoln Laboratory
Build & Release/DevOps Engineer
Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
State Street
Cloud Reliability Engineer, Project Manager - Part 2 of 2
Sun Jun 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
State Street
Build & Release/DevOps Engineer, Cloud Reliability Engineer, Project Manager - Part 1 of 2
Sun Jun 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Circuit Fabrication
CAE/CAD/CAM Designer, Process Engineer
Fri Jun 01 1990 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)