
Sheth Ketankumar
Hands on 8.5+ years of experience in digital ASIC/FPGA/SOC IP(Intellectual Property) RTL Design, Debugging, Verification and IP integration... | Bengaluru, Karnataka, India
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Sheth Ketankumar’s Emails sk****@go****.com
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Sheth Ketankumar’s Location Bengaluru, Karnataka, India
Sheth Ketankumar’s Expertise Hands on 8.5+ years of experience in digital ASIC/FPGA/SOC IP(Intellectual Property) RTL Design, Debugging, Verification and IP integration in SOC Experience with EDA tools : Altera Quartus-II, QSYS, Eclips, Mentor’s Modelsim, Simvision, SpyGlass, VCS, Design Compiler, Formality, TetraMax, Verdi, Jasper -Specialties in various protocols like : USB 3.1, USB 3.0, USB 2.0, Avalon, ULPI, UTMI, xHCI, AXI, Display Stream Compression -Experienced in following IP designing : - Display Stream Compression (Encoder + Decoder) - USB 3.1 Gen-2 Device Controller. - USB 3.0 Host Controller (Extensible Host Controller Interface - xHCI) - USB 2.0 Device Controller - USB 2.0 OTG ( Device block ) - HSIC ( High Speed Inter Chip ) Interface USB 2.0 Device - USB 2.0 Host BFM ( Block Functional Model ) - USB 3.0 Link-Layer,Proto-Layer,xHCI Designing - Basic Firmware Development using C - Familiar with language : System Verilog, Verilog, VHDL, C, HTML Specialties: System Verilog/Verilog based RTL Core Design, Lint, Clock Domain Crossing, Synthesis, SV/Verilog based Testbench development, Verification, Simulation, Logic Optimization, Timing closer, Trouble shooting. Key Skills : - Worked on entire ASIC digital IP design flow. Micro- architecture development, Deriving Function Specifications, RTL coding using Verilog and System Verilog, Lint, CDC, Functional verification, Synthesis, Timing closer, Logic optimization, Documentation, IP Release process, Customer support, Hardware debugging and testing. - I have good knowledge on Digital Design Concepts. - I have good understanding of the Verification Flow & Test bench architecture designing. - I have good debugging & problem solving skill. - I have hand on experience on NiosII processor and Altera FPGA system design, board bring up, hardware testing and debug. - I am always willing to learn new things. Education Qualification : B.E in Electronics and Communication (2009-2013) ,Government Engineering Collage Patan With 7.81 CGPA +Email-ID - [email protected] +Contact No - 7567639491
Sheth Ketankumar’s Current Industry Google
Sheth
Ketankumar’s Prior Industry
Google
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System Level Solutions
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Analog Devices
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Einfochips
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Synopsys
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Samsung Semiconductor
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Work Experience

Asic Rtl Design Engineer
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung Semiconductor
Senior Staff Engineer
Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Senior Asic Digital Design Engineer Sr. I
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Analog Devices
Asic Digital Design Engineer
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Asic Digital Design Engineer
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
System Level Solutions
Junior Asic Design Engineer
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Asic Rtl Design Engineer
— Present