Sheth Ketankumar

Sheth Ketankumar

Hands on 8.5+ years of experience in digital ASIC/FPGA/SOC IP(Intellectual Property) RTL Design, Debugging, Verification and IP integration... | Bengaluru, Karnataka, India

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Work Experience

Google

Asic Rtl Design Engineer

Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Samsung Semiconductor

Senior Staff Engineer

Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Synopsys

Senior Asic Digital Design Engineer Sr. I

Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Analog Devices

Asic Digital Design Engineer

Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Einfochips

Asic Digital Design Engineer

Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

System Level Solutions

Junior Asic Design Engineer

Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Google

Asic Rtl Design Engineer

— Present

Skills

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