
Siddesh Banakar
CORE COMPETENCIES : • Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming in C, Perl, Tcl,... | Bengaluru, Karnataka, India
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Siddesh Banakar’s Emails si****@in****.com
Siddesh Banakar’s Phone Numbers No phone number available.
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Siddesh Banakar’s Location Bengaluru, Karnataka, India
Siddesh Banakar’s Expertise CORE COMPETENCIES : • Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming in C, Perl, Tcl, Awk, Sed, Verilog, Makefile/Gnumake flow • Good Knowledge of ASIC flow (RTL to GDSII). • Static Timing Analysis, Floorplan, Placement, CTS, Routing, ECO, Physical verification, Synthesis, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. • An understanding of top view and cross sectional view of CMOS, Finfet, resistance, capacitance • Fabrication process • Basic understanding of RTL design (Verilog), Verification, EDA Tools : • ICC/ICC-2, Innovus/FE, Magma-Talus 1.2, ICV, Astro, Astro-Rail, • Star-RCXT, DC, PT, PT-SI, Composer Schematic, VirtuosoXL, Caliber • Hercules, VCS, Modelsim, Leda, Formality
Siddesh Banakar’s Current Industry Intel
Siddesh
Banakar’s Prior Industry
Acharya Institute Of Technology
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Rv Vlsi Design Center
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Smartplay Technologies
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Nvidia
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Qualcomm
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Concept2silicon Systems
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Synapse Design
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Mstar Semiconductor
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Amd
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Intel
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Wipro
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Work Experience

Intel
SoC Design Engineer
Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Sr. Physical Design Engineer - Consultant via Wipro
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro
Lead - Physical Design Engineer
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Physical Design Lead - consultant via Synapse
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Sr. Physical Design Engineer - consultant via Synapse
Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Synapse Design
Lead - Physical Design Engineer
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Mstar Semiconductor
Physical Design Engineer - Consultant via Synapse @ Taiwan
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Physical Design Engineer - Consultant via Concept2Silicon Systems
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Concept2silicon Systems
Physical Design Engineer - Lead
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Physical Design Engineer - Consultant via SmartPlay
Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Nvidia
Physical Design Engineer - Consultant via SmartPlay
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Smartplay Technologies
ASIC Physical Design Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Rv Vlsi Design Center
Physical Design Trainee
Tue Dec 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Rv Vlsi Design Center
Student
Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Acharya Institute Of Technology
Student
Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)