
Siddharth Sarangan
• Working for Access Financial Services at Ericsson as a Consultant ASIC Developer, working on Block level test bench.... | Stockholm, Stockholm, Sweden
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Siddharth Sarangan’s Emails ss****@qu****.com
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Siddharth Sarangan’s Location Stockholm, Stockholm, Sweden
Siddharth Sarangan’s Expertise • Working for Access Financial Services at Ericsson as a Consultant ASIC Developer, working on Block level test bench. • Previously worked for Qualcomm India as Lead Engineer Sr. (Design Verification) for WLAN team and have worked on Block level and integration level test benches involving complex WLAN and WLAN Co-existence features. • Previously worked for Intel India as Component Designer – Design verification responsible for Validation of multiple units in Integrated Graphics across 4 projects. • Owned and successfully delivered control path blocks like WLAN(s) – BT – LTE Co-existence , Dynamic Payload aggregation controller • Owned and successfully delivered critical integration level features like 802.11ac/802.11ax beamforming , beamformee , Multi User OFDMA which are integral part of the latest chipset. • Owned and successfully delivered data path blocks like Register Reinitialization Engine , Instruction Cache. • Good Knowledge on 802.11 IEEE standards (a,b,n,ac,ax). • Exceptional communication and collaboration skills with proficiency at grasping new technical concepts quickly and utilize the same in a productive manner.
Siddharth Sarangan’s Current Industry Ericsson
Siddharth
Sarangan’s Prior Industry
Intel India Technology
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Qualcomm
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Ericsson
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Work Experience

Ericsson
ASIC Developer
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Lead Engineer Senior
Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Senior Engineer
Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Engineer
Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel India Technology
Validation Engineer
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)