Siddharth Sawant
ASIC Hardware engineering and program management leader offering 14 years of experience in product and foundry businesses driving... | 180 Alicante DriveUnit 201, San Jose, United States
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Siddharth Sawant’s Location 180 Alicante DriveUnit 201, San Jose, United States
Siddharth Sawant’s Expertise ASIC Hardware engineering and program management leader offering 14 years of experience in product and foundry businesses driving ASIC/SoC programs, pre and post-silicon product development, digital methodology development, customer, EDA & IP, and vendor management. ► Supported 100+ customers across 10+ tech nodes for Automotive, Datacenter, SatCom, GPU applications ► Big-tech and start-up experience of leading ASIC programs towards successful tape-out and first-pass silicon ► Engineer turned TPM with technical experience spanning RTL to GDSII, implementation, design flows, LEC, library characterization, STA timing and margins, Spice and Monte-Carlo simulations, aging ► Presented at multiple industry conferences such as SNUG, CDNLive, Tau, and DAC as an industry expert and invited speaker on Automotive Aging reliability and timing flows
Siddharth Sawant’s Current Industry Meta
Siddharth
Sawant’s Prior Industry
Microchip Technology
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Intel
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Qualcomm
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Globalfoundries
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Aeva
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Meta
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Work Experience
Meta
Silicon Technical Program Management - AR/VR Reality Labs
Thu Feb 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Aeva
Technical Program Management, Silicon
Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Senior Member Of Technical Staff (Hardware Lead)
Mon Jun 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Member of Technical Staff (Hardware Lead)
Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Design Implementation Engineer(Synthesis, timing(STA), Conformal LEC- Implementation Engineer)
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Graphics Hardware Engineer
Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Microchip Technology
Design Engineer
Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Microchip Technology
Analog Engineering Intern
Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Siddharth Sawant Email Addresses
FAQ About Siddharth Sawant
-
Siddharth Sawant is located at
180 Alicante DriveUnit 201, San Jose, United States -
Siddharth Sawant is a
ASIC Hardware engineering and program management leader offering 14 years of experience in product and foundry businesses driving ASIC/SoC programs, pre and post-silicon product development, digital methodology development, customer, EDA & IP, and vendor management. ► Supported 100+ customers across 10+ tech nodes for Automotive, Datacenter, SatCom, GPU applications ► Big-tech and start-up experience of leading ASIC programs towards successful tape-out and first-pass silicon ► Engineer turned TPM with technical experience spanning RTL to GDSII, implementation, design flows, LEC, library characterization, STA timing and margins, Spice and Monte-Carlo simulations, aging ► Presented at multiple industry conferences such as SNUG, CDNLive, Tau, and DAC as an industry expert and invited speaker on Automotive Aging reliability and timing flows Meta -
Siddharth Sawant currently works in the
Meta -
Siddharth Sawant specializes in
ASIC Hardware engineering and program management leader offering 14 years of experience in product and foundry businesses driving ASIC/SoC programs, pre and post-silicon product development, digital methodology development, customer, EDA & IP, and vendor management. ► Supported 100+ customers across 10+ tech nodes for Automotive, Datacenter, SatCom, GPU applications ► Big-tech and start-up experience of leading ASIC programs towards successful tape-out and first-pass silicon ► Engineer turned TPM with technical experience spanning RTL to GDSII, implementation, design flows, LEC, library characterization, STA timing and margins, Spice and Monte-Carlo simulations, aging ► Presented at multiple industry conferences such as SNUG, CDNLive, Tau, and DAC as an industry expert and invited speaker on Automotive Aging reliability and timing flows -
Siddharth Sawant speaks the following languages:
No languages available. -
Siddharth Sawant has prior experience in the following industries:
Aeva , Globalfoundries , Globalfoundries , Qualcomm , Intel , Microchip Technology , Microchip Technology -
Siddharth Sawant has the following professional experience:
Meta , Aeva , Globalfoundries , Globalfoundries , Qualcomm , Intel , Microchip Technology , Microchip Technology . -
You can view Siddharth Sawant’s
LinkedIn profile at LinkedIn URL. -
Siddharth Sawant’s work email addresses are
[email protected] . -
Siddharth Sawant works at
Meta
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