
Silvia Jaeckel
Design engineer with proven track record to first-pass success. Hands-on experience in digital and mixed signal designs in... | Divide, Colorado, United States
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Silvia Jaeckel’s Emails si****@tr****.com
Silvia Jaeckel’s Phone Numbers 1719351****
Social Media
Silvia Jaeckel’s Location Divide, Colorado, United States
Silvia Jaeckel’s Expertise Design engineer with proven track record to first-pass success. Hands-on experience in digital and mixed signal designs in a variety of applications: high-speed storage, low-power medical, and low-cost automotive industries. Expert knowledge in SOC design including product requirements definition, architecture specification, RTL implementation and verification, DFT, and physical design steps: synthesis, static timing analysis, logic equivalency checking, place-and-route and test vector generation. Hands-on experience with integrating 3rd-party IP such as processors and memories. Skilled project lead with demonstrated success in managing diverse functional and geographically dispersed teams. Demonstrated skills in innovative development and problem-solving: eight patents in digital design. Strong scripting skills. Tools: * Simulation Mentor Graphics Modelsim, Cadence NCV, * SYN Synopsys DesignCompiler, Cadence RTL Compiler, Incentia DesignCraft * STA: Synopsys Primetime, Cadence Tempus, Incentia TimeCraft * LEC: Synopsys Formality, Cadence Conformal, * PNR: Cadence Innovus * ATPG: Synopsys Tetramax, Mentor Graphics Tessent
Silvia Jaeckel’s Current Industry Hausberg
Silvia
Jaeckel’s Prior Industry
Ford Microelectronics
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Lsi Logic
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On Semiconductor
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Treehouse Design
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Hausberg
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Work Experience

Hausberg
Owner of Hausberg Ltd.
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Treehouse Design
Project Lead / Architect / Digital Backend Methodology Lead / Senior IC Design Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
On Semiconductor
Project Lead / Principal IC Design Engineer
Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi Logic
Staff IC Design Engineer
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Ford Microelectronics
IC Design Engineer
Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)