
Srinivas Rajendra
Senior Manager in the NAND IO design group at Western Digital with expertise in the following fields: ... | 928 Valencia Drive, Milpitas, United States
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Srinivas Rajendra’s Location 928 Valencia Drive, Milpitas, United States
Srinivas Rajendra’s Expertise Senior Manager in the NAND IO design group at Western Digital with expertise in the following fields: High speed Transmitter and Receivers with equalization techniques like CTLE/DFE/pre-emphasis/de-emphasis CMOS/CML clock distribution network ZQ calibration, On die termination, Duty cycle correction circuits Good grasp of Analog/Mixed signal blocks like Amplifiers/equalization/PLL/LDO/Bandgap/etc AC Timing simulations & full chip spice verification for DDR2/3/4/5 NAND Flash Memory. Strong grasp on high speed custom circuit design methodologies, power grid planning and optimization, dynamic power droop simulations, ESD clamp design Experience in working with product, application & Signal Integrity teams to enable products with higher speeds than targets Experience with multiple tapeouts and Silicon debug to identify failure mechanisms and high-speed probing Supervised layout activities to meet design guidelines. Interacted closely with device engineers to define transistor requirements for next-gen memory Excellent communication skills ensuring effective coordination among multiple teams in different geographies. Over 10 patents filed/pending
Srinivas Rajendra’s Current Industry Nvidia
Srinivas
Rajendra’s Prior Industry
University Of Southern California
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Forza Silicon
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Sandisk
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Western Digital
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Nvidia
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Work Experience

Nvidia
Sr Mixed Signal Design Engineer
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Western Digital
Sr Manager, IO Design
Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Western Digital
Manager, Electronic Design Engineering, I/O Design
Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Western Digital
Principal Engineer
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Western Digital
Principal Engineer
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Western Digital
Staff Engineer
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Sandisk
Design Engineer II
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Sandisk
Intern
Sat Feb 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Forza Silicon
Analog Design Engineering Intern
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
University Of Southern California
Student
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)