Steve Gibson

FAQ About Steve Gibson

• What is Steve Gibson's address?

  Steve Gibson is located at
  Albuquerque, Albuquerque, United States

• What is Steve Gibson's job title?

  Steve Gibson is a
  •Perform electrical tests at the component level in accordance with Military Standards and established work procedures •Perform environmental stress tests using humidity and pressure chambers •Record test results, maintain work logs and status reports in accordance with company work instructions. •Responsible for the proper use and care of equipment and maintaining a clean and orderly work area. •Perform limited preventative maintenance functions on equipment. •Follow and support Lean and 5S initiatives. •Perform miscellaneous job-related duties as assigned. RESPONSIBILITIES: 300 mm Logic Sort Working Group leader, test development, test integration, project management, data analysis, system preparation, material disposition. Owned IO test development including vixvox, DDR, OPI and leakage on Intel’s Broadwell product in preparation for Product Reliability Qual. Helped on shops, Sort Interface Unit (SIU) definition files, PLL, power tests and test program integration. Installed tests on six previous products and worked on first silicon events in New Mexico, Oregon and Israel. Generated Perl scripts for material disposition, test validation and data analysis. Mentored junior engineers on product test development and manufacturing. Researched and set up WinCVS GUI for revision control of SoC test code in Arizona CVS databases for 2 products. Spent 6 months as Site PE in D1C Oregon Sort operations to ensure systems were available for Product Engineers in Arizona and Ireland to debug chipset product. Owned material dispositioning and statistical bin limits. Assisted product transfer to Aloha Sort and owned the transfer of the product to Sort 11X in New Mexico, all on schedule. Chaired Sort Working Group (SWG) containing members from product test development in Arizona and New Mexico Fab Engineering to drive test releases. Published white papers and monitored 300 mm product movement on schedule through wafer sort.RESPONSIBILITIES: Sort Working Group leader, 200 mm Flash memory test software generation and release, data analysis. As SWG leader, scheduled and ran weekly meetings with local and divisional engineers and conducted code reviews, split lot experiments, statistical data reviews on Engineering and test program releases in Production. Converted test programs in C from Verigy (Agilent) V1316 platform to V4400, which generated a 50% capacity increase through test time reduction and increased touchdown density on the V4400 platform. Conversions also enabled two other Sort sites to test their own wafers, negating the need to send their wafers to New Mexico for testing. Launched and maintained sole Sort site for wafer sales testing on 128M Flash memory product on Verigy (Agilent) V4400 platform with four external customer line items. Trained two other engineers as new products were introduced.RESPONSIBILITIES: Solved sort-to-fab and package test-to-sort issues on 150 mm Flash memory, implemented test program revisions, chaired Test Control Change Board and Sort/Etest Transfer (to Israel) Team, continued role as Sort Year 2000 site coordinator. Researched Vt issues on certification wafer to find that one block was not programming properly on many dice. Had memory arrays on the wafer stripped back for liquid crystal emission analysis. Found adjacent columns connected by defects, causing them to leak charge after programming. This discovery led to the installation of a dual leaky column test on the product. Established working group to research elevated cam programming fallout on 28F800 product and solved it by modifying C code. Also modified APG code to create and implement inverse checkerboard pattern, which enabled package test to detect charge gain/loss at Post Burn-In (PBI), motivated by customer returns. Led Sort Department through a quiet New Year’s 2000 transition.RESPONSIBILITIES: Managed Verigy (Versatest) V1002/V1004 150 mm Flash memory testers, coordinated Year 2000 preparation for Sort Department. Used test programming knowledge to create scripts for forcing voltages on selectable tester channels. Trained technicians to use these scripts for troubleshooting interface hardware issues. Resolved Agilent tester and sort controller issues. Owned installation of tester software, procedures and first-die targets. Managed the relocation of testers across two test floors. Led a team of Sort engineers to inventory and document Year 2000 sensitivities on all hardware and software. Reported this data to cross-site team led by the Site manager. Managed test and upgrade deployment of that inventory for Flash Sort manufacturing.RESPONSIBILITIES: Provided interface hardware solutions for new Flash memory product testing. Procured, reviewed, validated and approved 31 PCB designs resulting in 242 assemblies delivered to Folsom, CA, New Mexico and Philippines for Sort and Class engineering use and manufacturing. Worked with PCB supplier to deliver Failure Analysis (FA) hardware with conformal coating to protect socket pins from leaking current when cycled from cold to room temperature. This became the new standard for FA and package test hardware and allowed us to remove a cleaning step from our preventative maintenance, which dramatically improved uptime. IEC ANALYSIS & TESTING LABORATORY

• What industry does Steve Gibson currently work in?

  Steve Gibson currently works in the
  IEC ANALYSIS & TESTING LABORATORY

• What is Steve Gibson's area of expertise?

  Steve Gibson specializes in
  •Perform electrical tests at the component level in accordance with Military Standards and established work procedures •Perform environmental stress tests using humidity and pressure chambers •Record test results, maintain work logs and status reports in accordance with company work instructions. •Responsible for the proper use and care of equipment and maintaining a clean and orderly work area. •Perform limited preventative maintenance functions on equipment. •Follow and support Lean and 5S initiatives. •Perform miscellaneous job-related duties as assigned. RESPONSIBILITIES: 300 mm Logic Sort Working Group leader, test development, test integration, project management, data analysis, system preparation, material disposition. Owned IO test development including vixvox, DDR, OPI and leakage on Intel’s Broadwell product in preparation for Product Reliability Qual. Helped on shops, Sort Interface Unit (SIU) definition files, PLL, power tests and test program integration. Installed tests on six previous products and worked on first silicon events in New Mexico, Oregon and Israel. Generated Perl scripts for material disposition, test validation and data analysis. Mentored junior engineers on product test development and manufacturing. Researched and set up WinCVS GUI for revision control of SoC test code in Arizona CVS databases for 2 products. Spent 6 months as Site PE in D1C Oregon Sort operations to ensure systems were available for Product Engineers in Arizona and Ireland to debug chipset product. Owned material dispositioning and statistical bin limits. Assisted product transfer to Aloha Sort and owned the transfer of the product to Sort 11X in New Mexico, all on schedule. Chaired Sort Working Group (SWG) containing members from product test development in Arizona and New Mexico Fab Engineering to drive test releases. Published white papers and monitored 300 mm product movement on schedule through wafer sort.RESPONSIBILITIES: Sort Working Group leader, 200 mm Flash memory test software generation and release, data analysis. As SWG leader, scheduled and ran weekly meetings with local and divisional engineers and conducted code reviews, split lot experiments, statistical data reviews on Engineering and test program releases in Production. Converted test programs in C from Verigy (Agilent) V1316 platform to V4400, which generated a 50% capacity increase through test time reduction and increased touchdown density on the V4400 platform. Conversions also enabled two other Sort sites to test their own wafers, negating the need to send their wafers to New Mexico for testing. Launched and maintained sole Sort site for wafer sales testing on 128M Flash memory product on Verigy (Agilent) V4400 platform with four external customer line items. Trained two other engineers as new products were introduced.RESPONSIBILITIES: Solved sort-to-fab and package test-to-sort issues on 150 mm Flash memory, implemented test program revisions, chaired Test Control Change Board and Sort/Etest Transfer (to Israel) Team, continued role as Sort Year 2000 site coordinator. Researched Vt issues on certification wafer to find that one block was not programming properly on many dice. Had memory arrays on the wafer stripped back for liquid crystal emission analysis. Found adjacent columns connected by defects, causing them to leak charge after programming. This discovery led to the installation of a dual leaky column test on the product. Established working group to research elevated cam programming fallout on 28F800 product and solved it by modifying C code. Also modified APG code to create and implement inverse checkerboard pattern, which enabled package test to detect charge gain/loss at Post Burn-In (PBI), motivated by customer returns. Led Sort Department through a quiet New Year’s 2000 transition.RESPONSIBILITIES: Managed Verigy (Versatest) V1002/V1004 150 mm Flash memory testers, coordinated Year 2000 preparation for Sort Department. Used test programming knowledge to create scripts for forcing voltages on selectable tester channels. Trained technicians to use these scripts for troubleshooting interface hardware issues. Resolved Agilent tester and sort controller issues. Owned installation of tester software, procedures and first-die targets. Managed the relocation of testers across two test floors. Led a team of Sort engineers to inventory and document Year 2000 sensitivities on all hardware and software. Reported this data to cross-site team led by the Site manager. Managed test and upgrade deployment of that inventory for Flash Sort manufacturing.RESPONSIBILITIES: Provided interface hardware solutions for new Flash memory product testing. Procured, reviewed, validated and approved 31 PCB designs resulting in 242 assemblies delivered to Folsom, CA, New Mexico and Philippines for Sort and Class engineering use and manufacturing. Worked with PCB supplier to deliver Failure Analysis (FA) hardware with conformal coating to protect socket pins from leaking current when cycled from cold to room temperature. This became the new standard for FA and package test hardware and allowed us to remove a cleaning step from our preventative maintenance, which dramatically improved uptime.

• Which languages does Steve Gibson speak? 

  Steve Gibson speaks the following languages:
  No languages available.

• Which industries has Steve Gibson previously worked in?   

  Steve Gibson has prior experience in the following industries:
  IEC ANALYSIS & TESTING LABORATORY , Intel Corporation , Intel Corporation , Intel Corporation , Intel Corporation , Intel Corporation

• What is Steve Gibson’s work experience?  

  Steve Gibson has the following professional experience:
  IEC ANALYSIS & TESTING LABORATORY , Intel Corporation , Intel Corporation , Intel Corporation , Intel Corporation , Intel Corporation .

• How can I find Steve Gibson on LinkedIn?  

  You can view Steve Gibson’s
  LinkedIn profile at LinkedIn URL.

• What are Steve Gibson’s work email addresses?  

  Steve Gibson’s work email addresses are
  [email protected] .

• What company does Steve Gibson work for?  

  Steve Gibson works at
  IEC ANALYSIS & TESTING LABORATORY