Suresh Pachha
– Physical implementation from RTL to GDS including Synthesis, PnR, timing closure and physical verification – Full... | Bengaluru, Karnataka, India
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Suresh Pachha’s Emails su****@in****.com
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Suresh Pachha’s Location Bengaluru, Karnataka, India
Suresh Pachha’s Expertise – Physical implementation from RTL to GDS including Synthesis, PnR, timing closure and physical verification – Full Chip/SubSystem Synthesis, DP, Block closure, integration & physical verification – Full Chip/SubSystem constraints development, IO budgeting & timing closure – High speed clock tree/mesh planning, distribution, methodology & skew analysis – Experience in various technology nodes (65nm 7nm) with successful tape-out of multiple high-speed/low-power microprocessors.
Suresh Pachha’s Current Industry Intel
Suresh
Pachha’s Prior Industry
Wipro Technologies
|
Texas Instruments
|
Broadcom
|
Intel
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Work Experience
Intel
Soc Design Engineer
Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Broadcom
Senior Staff Engineer
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Lead Ddr Engineer
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro Technologies
Senior Physical Design Engineer
Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Suresh Pachha Email Addresses
FAQ About Suresh Pachha
-
Suresh Pachha is located at
Bengaluru, Karnataka, India -
Suresh Pachha is a
– Physical implementation from RTL to GDS including Synthesis, PnR, timing closure and physical verification – Full Chip/SubSystem Synthesis, DP, Block closure, integration & physical verification – Full Chip/SubSystem constraints development, IO budgeting & timing closure – High speed clock tree/mesh planning, distribution, methodology & skew analysis – Experience in various technology nodes (65nm 7nm) with successful tape-out of multiple high-speed/low-power microprocessors. Intel -
Suresh Pachha currently works in the
Intel -
Suresh Pachha specializes in
– Physical implementation from RTL to GDS including Synthesis, PnR, timing closure and physical verification – Full Chip/SubSystem Synthesis, DP, Block closure, integration & physical verification – Full Chip/SubSystem constraints development, IO budgeting & timing closure – High speed clock tree/mesh planning, distribution, methodology & skew analysis – Experience in various technology nodes (65nm 7nm) with successful tape-out of multiple high-speed/low-power microprocessors. -
Suresh Pachha speaks the following languages:
No languages available. -
Suresh Pachha has prior experience in the following industries:
Broadcom , Texas Instruments , Wipro Technologies -
Suresh Pachha has the following professional experience:
Intel , Broadcom , Texas Instruments , Wipro Technologies . -
You can view Suresh Pachha’s
LinkedIn profile at LinkedIn URL. -
Suresh Pachha’s work email addresses are
[email protected] . -
Suresh Pachha works at
Intel
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