Tie Wang
CAREER SUMMARY: • Wafer Level Packaging design, process development and integration. • Fan-Out WLP and Embedded IC module technology development. •... | San Francisco, California, United States
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Tie Wang’s Emails ti****@ma****.com
Tie Wang’s Phone Numbers No phone number available.
Social Media
Tie Wang’s Location San Francisco, California, United States
Tie Wang’s Expertise CAREER SUMMARY: • Wafer Level Packaging design, process development and integration. • Fan-Out WLP and Embedded IC module technology development. • Flip Chip assembly process development and underfill material formulation. • Wafer bumping - including copper pillar bumping. • Silicon Thru-Via and 3D interconnect technology. • 18+ years of experience in the USA and S-E Asia in Microelectronics Industries. • 7 US Patents. HIGHLIGHTS: •Strong blending of technology, people & organization skill and market knowledge. •Off-shore manufacturing and business development
Tie Wang’s Current Industry Apple
Tie
Wang’s Prior Industry
Advanpack Solutions
|
Stats Chippac
|
Ablestik Laboratories
|
Allvia
|
Maxim Integrated
|
Qualcomm
|
Apple
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Work Experience
Apple
IC Packaging Integration Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
RF Front-End Module Packaging Engineer
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Maxim Integrated
Principal Member of Technical Staff
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Maxim Integrated
Senior Member of Technical Staff
Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Allvia
Director, Back-end Development and Operation
Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Ablestik Laboratories
Team Leader, Advanced Flip Chip Packaging Material
Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Stats Chippac
Member of Technical Staff
Sun Sep 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Advanpack Solutions
Technical Manager
Fri Aug 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Tie Wang Email Addresses
FAQ About Tie Wang
-
Tie Wang is located at
San Francisco, California, United States -
Tie Wang is a
CAREER SUMMARY: • Wafer Level Packaging design, process development and integration. • Fan-Out WLP and Embedded IC module technology development. • Flip Chip assembly process development and underfill material formulation. • Wafer bumping - including copper pillar bumping. • Silicon Thru-Via and 3D interconnect technology. • 18+ years of experience in the USA and S-E Asia in Microelectronics Industries. • 7 US Patents. HIGHLIGHTS: •Strong blending of technology, people & organization skill and market knowledge. •Off-shore manufacturing and business development Apple -
Tie Wang currently works in the
Apple -
Tie Wang specializes in
CAREER SUMMARY: • Wafer Level Packaging design, process development and integration. • Fan-Out WLP and Embedded IC module technology development. • Flip Chip assembly process development and underfill material formulation. • Wafer bumping - including copper pillar bumping. • Silicon Thru-Via and 3D interconnect technology. • 18+ years of experience in the USA and S-E Asia in Microelectronics Industries. • 7 US Patents. HIGHLIGHTS: •Strong blending of technology, people & organization skill and market knowledge. •Off-shore manufacturing and business development -
Tie Wang speaks the following languages:
No languages available. -
Tie Wang has prior experience in the following industries:
Qualcomm , Maxim Integrated , Maxim Integrated , Allvia , Ablestik Laboratories , Stats Chippac , Advanpack Solutions -
Tie Wang has the following professional experience:
Apple , Qualcomm , Maxim Integrated , Maxim Integrated , Allvia , Ablestik Laboratories , Stats Chippac , Advanpack Solutions . -
You can view Tie Wang’s
LinkedIn profile at LinkedIn URL. -
Tie Wang’s work email addresses are
[email protected] . -
Tie Wang works at
Apple
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