
Trong Nguyen
20 years experience in RFIC Analog IC Design / Layout. Responsible for design and test of advance CMOS... | Winter Springs, Florida, United States
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Trong Nguyen’s Location Winter Springs, Florida, United States
Trong Nguyen’s Expertise 20 years experience in RFIC Analog IC Design / Layout. Responsible for design and test of advance CMOS - FINFET Analog and RF platforms. Strong technical and problem-solving skills with an expert eye for finding solutions in difficult design requirements (KPI = Key Performance Indicator). Designed and developed a wide collection of wireless communication devices ultilize for internet and mobile cell phone applications included High Frequency RF devices. LNAs, Power Amp, Mixer, et al. Architecture and Floorplan from chip level to block level layout including top level integration and pad ring layout for RF/high speed blocks and importing of digital layouts into top level integration. Coordination of off-site layout block resources and support with team members. Preparation of technical reviews and product documentation. Worked with cross functional teams to deliver high quality IC Products. Conduct tape-out verification tasks which include; DRC and LVS Conduct post-layout simulation to verify sub-block function of Analog block OpAmp, BandGap, etc... and RF block LNA, Phase-Shifter, Pre-Scalar, VCO, LO-Buffer, Mixer, AGC, PA, etc... Extensive knowledge of implemented layout technique to eliminate I and Q amplitude imbalance and suppress Side Band re-growth. Extensive knowledge of electrical issues such as EM, coupling and RC, substrate cross talk, LO Re-Rad. Extensive knowledge implementing common centroid-device matching techniques minimizing process gradient errors such as IQ mismatch and DC offset while enhancing full chip performance and improvement of mass production yield. Responsibilities include performing proof of concept of advanced RFIC Analog Mixed signal designs and Mixed Signal Processing circuitry. Executing full scale design simulations which include schematic-to-layout verifications. Flexible and effective team member with a strong ability to work independently as to research and develop new design concept.
Trong Nguyen’s Current Industry Intel
Trong
Nguyen’s Prior Industry
Signal Technologies
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Schwartz Electro Optics
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Parkervision
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Intel
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Work Experience

Intel
Senior RFIC Physical Design Engineer
Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Parkervision
RFIC Layout/Design Engineer
Wed Mar 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Schwartz Electro Optics
Analog Application Design Engineer
Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Signal Technologies
Analog IC Design Engineer
Mon May 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)