Umang Angrish
VLSI Domain Skills HDLs: Verilog HVL: System Verilog,UVM Scripting Language: shell scripting (linux) EDA Tool: Xilinx ISE, Modelsim Domain: ASIC/FPGA Design Flow, Digital Design... | South Delhi, Delhi, India
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Umang Angrish’s Emails ua****@ca****.com
Umang Angrish’s Phone Numbers No phone number available.
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Umang Angrish’s Location South Delhi, Delhi, India
Umang Angrish’s Expertise VLSI Domain Skills HDLs: Verilog HVL: System Verilog,UVM Scripting Language: shell scripting (linux) EDA Tool: Xilinx ISE, Modelsim Domain: ASIC/FPGA Design Flow, Digital Design & Verification methodologies Knowledge: FSM based design, Simulation, Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog
Umang Angrish’s Current Industry Cadence Design Systems
Umang
Angrish’s Prior Industry
Cadence Design Systems
|
Sofcon
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None
|
Chegg
|
Confidential
|
Mirafra Technologies
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Work Experience
Cadence Design Systems
Product Validation Engineer Ii
Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mirafra Technologies
Verification Engineer
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Confidential
Verification Engineer
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Chegg
Q&A Expert
Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
None
None
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Intern-Software Engineer
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Sofcon
Trainee
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Product Validation Engineer Ii
— PresentSkills
Languages
Umang Angrish Email Addresses
FAQ About Umang Angrish
-
Umang Angrish is located at
South Delhi, Delhi, India -
Umang Angrish is a
VLSI Domain Skills HDLs: Verilog HVL: System Verilog,UVM Scripting Language: shell scripting (linux) EDA Tool: Xilinx ISE, Modelsim Domain: ASIC/FPGA Design Flow, Digital Design & Verification methodologies Knowledge: FSM based design, Simulation, Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Cadence Design Systems -
Umang Angrish currently works in the
Cadence Design Systems -
Umang Angrish specializes in
VLSI Domain Skills HDLs: Verilog HVL: System Verilog,UVM Scripting Language: shell scripting (linux) EDA Tool: Xilinx ISE, Modelsim Domain: ASIC/FPGA Design Flow, Digital Design & Verification methodologies Knowledge: FSM based design, Simulation, Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog -
Umang Angrish speaks the following languages:
No languages available. -
Umang Angrish has prior experience in the following industries:
Mirafra Technologies , Confidential , Chegg , None , Cadence Design Systems , Sofcon -
Umang Angrish has the following professional experience:
Cadence Design Systems , Mirafra Technologies , Confidential , Chegg , None , Cadence Design Systems , Sofcon , Cadence Design Systems . -
You can view Umang Angrish’s
LinkedIn profile at LinkedIn URL. -
Umang Angrish’s work email addresses are
[email protected] . -
Umang Angrish works at
Cadence Design Systems
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