
Veeresh S
Successfully Leading and Managing layout team in the Emerging Memory group. Expertise in Memory/ Analog/ Mixed Signal Layout... | Greater Sacramento, Greater Sacramento, United States
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Veeresh S’s Emails vs****@mi****.com
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Veeresh S’s Location Greater Sacramento, Greater Sacramento, United States
Veeresh S’s Expertise Successfully Leading and Managing layout team in the Emerging Memory group. Expertise in Memory/ Analog/ Mixed Signal Layout Designs. Worked on custom layouts, pitch cells (Sense Amp, X/Y Decoders), chip level layouts, path finding, Auto Place and Route tools, verification against design tools, parasitic matching and programming for layout automation, mainly focused on Memory, Data Converters and its sub-blocks, design of test structures for process characterization. Expertise in Layout Design of Memory core, array, pitch, periphery designs, Data converters (ADC), reference generators, PLL, Differential Amplifiers, ESD Circuits, IO Ring, Fuse Layouts, Full Chip spin off works and other analog blocks.
Veeresh S’s Current Industry Micron Technology
Veeresh
S’s Prior Industry
Karmic Worked For Texas Instruments
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Micron Technology
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Work Experience

Micron Technology
Layout Lead
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Micron Technology
Layout Design Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Karmic Worked For Texas Instruments
Member of Technical Staff
Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)