
Vishal Kulshrestha
M. Tech from BITS Pilani with more than 20 years of Industry experience in IO and mixed signal... | Hyderabad, Hyderabad, India
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Vishal Kulshrestha’s Emails vi****@st****.com
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Vishal Kulshrestha’s Location Hyderabad, Hyderabad, India
Vishal Kulshrestha’s Expertise M. Tech from BITS Pilani with more than 20 years of Industry experience in IO and mixed signal design and development including. Managing the circuit design group of FPGA division at Microchip. Technical lead in GPIO/HSIO design including DDR IO circuit design. Experience in Full product development cycle for IO and peripherals and their integration on to ASIC/SOC/FPGA. Experience in DDRPHY implementation in SOC with its interface, Training IP & DFI interface with APB bus, Read/Write memory procedures, SGMII PHY implementation in SOC with dynamic training IP at PCS level using10 bit interface interfacing with controller Experience in design verification of 12.5 Gbps SERDES in 28nm with CTLE/DFE equalization for receivers and its integration into PCIESS/GPSS sub systems with quad channel. Design and validation of General purpose and High Speed IOs, Slew rate-controlled IO, SDIO, eMMC, I2C, DDR3/DDR4, HSTL, SSTL, Fail-safe IO, LVDS, MIPI, LVDS, LVPECL and other standard IOs. Design Experience with 0.18um,0.15um,0.13um,90nm, 65nm, 45nm and 32/28nm planar technologies, 28nm FDSOI Experience in ESD & Latch up strategy, IO ring design, Pad ring reviews of SOC’s/Test-chips in multiple technologies Responsible for mentoring co-engineers in planning, execution and problem solving and Supervision of Layout design engineer for different projects in multiple nodes. Working experience with cross functional teams to optimize the designs and to provide support in various stages of SOC/FPGA development Responsible for technical documentation, flow development and understanding of design methodologies/issues and validation for the same.
Vishal Kulshrestha’s Current Industry Microchip Technology
Vishal
Kulshrestha’s Prior Industry
Microchip Technology
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Bharat Electronics
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St Microelectronics
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Microsemi
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Work Experience

Microchip Technology
Engineering Manager - Circuit Design
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Microsemi
Senior Staff Design Engineer
Sun Nov 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
St Microelectronics
Staff Design Engineer
Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Bharat Electronics
Design Engineer
Fri Mar 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Microchip Technology
Engineering Manager - Circuit Design
— Present