
Vivek Gupta
*Skill Set listed on United Kingdom Shortage Occupation list. • IP Verification using UVM/SV-based environment involving Testbench creation and... | Cambridge, England, United Kingdom
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Vivek Gupta’s Emails vi****@ar****.com
Vivek Gupta’s Phone Numbers No phone number available.
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Vivek Gupta’s Location Cambridge, England, United Kingdom
Vivek Gupta’s Expertise *Skill Set listed on United Kingdom Shortage Occupation list. • IP Verification using UVM/SV-based environment involving Testbench creation and Coverage Metrics writing. • Languages/Methodologies: System Verilog, UVM (Universal Verification Methodology), Verilog, and C. • Proficient in Ethernet, TCP/IP, AMBA (AXI), proprietary protocols (specific to supercomputer projects), IOSF, and basics of PCIe. • Hands-on experience with tools such as VCS, DVE, SIMVISION, NCSIM (irun), IMC (coverage), QuestaSim, Netbatch, Venus, Granite, GIT, SVN, and Perforce. • Proficient in PERL scripting language. • Processor verification using YAML (Yet Another Markup Language: Similar to assembly). • Successfully contributed to the verification of NB-IoT chips. PS - Skill Set listed on the United Kingdom Shortage Occupation list.
Vivek Gupta’s Current Industry Arm
Vivek
Gupta’s Prior Industry
Telecom Network Solutions
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Wipro
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Hcl Technologies
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Nec Technologies
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Intel
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Arm
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Amd
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Work Experience

Arm
Senior Design Verification Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amd
Senior Design Verification Engineer
Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Arm
Senior Design Verification Engineer
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Verification Engineer
Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Nec Technologies
Verification Engineer
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Hcl Technologies
Lead Engineer (Design Verification Engineer)
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro
Project Engineer (Design Verification Engineer)
Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Telecom Network Solutions
Trainee
Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)