
Wen-Hsien Chuang
- Responsible for root cause understanding of inline and end-of-line (EOL) process defects, reliability fails, device performance, circuit... | Portland, Oregon, United States
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Wen-Hsien Chuang’s Location Portland, Oregon, United States
Wen-Hsien Chuang’s Expertise - Responsible for root cause understanding of inline and end-of-line (EOL) process defects, reliability fails, device performance, circuit design bugs, and circuit functionality of Intel 22nm, 14nm, and 10nm SOC products, graphic products, and FPGA products - Responsible (co-own) for new SoC process development and process/product/reliability yield improvement with yield, module, and integration team - Responsible for debug and failure analysis technique enabling to support Intel process/product development Previous experience: - Responsible for failure analysis and device simulation on Intel 45nm, 32nm, 22nm devices for process yield and reliability improvement - Responsible for circuit debug on Intel CPU and chipset products for design bug fix with design and test content team - Competitive analysis on CPU/GPU and SOC devices including Intel 90nm, 65nm, 45nm, 22nm devices, TSMC 55nm, 40nm, 28nm devices, AMD 65nm,45nm devices, and Samsung 45nm devices to bench-mark transistor performance from different companies and understand design features used on different products Professional skills: - Process and product debug for yield and reliability improvement - Process failure modeling for process DOE and sensitive defect layout identification - Debug technique development and tool enabling for new process, 3D packaging, and new product platforms - Device electrical characterization and competitive analysis to bench-mark transistor performance from different companies - SOC/CPU/FPGA DFT testing (functional, scan, cache, and IO) and circuit debug
Wen-Hsien Chuang’s Current Industry Tsmc
Wen-Hsien
Chuang’s Prior Industry
Intel
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Tsmc
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Work Experience

Tsmc
Director
Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Engineering Td Manager
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Failure Isolation/Analysis Technology Development Engineer
Wed Jun 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Engineering Td Manager
— Present