
Yi Zhao
Comprehensive RFIC design manager/engineer with years of experiences both as individual contributor and as chip lead of complex... | Cupertino, California, United States
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Yi Zhao’s Emails yi****@ap****.com
Yi Zhao’s Phone Numbers No phone number available.
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Yi Zhao’s Location Cupertino, California, United States
Yi Zhao’s Expertise Comprehensive RFIC design manager/engineer with years of experiences both as individual contributor and as chip lead of complex wireless SoCs. Pre-silicon and post-silicon chip lead of SoC projects. Experienced in cross functional collaboration with hundreds of people covering design, layout, DI, DV, DMS, PMU, PD, DFT, ATE, lab bring up and system characterization. Strong in schedule management, execution power and attention to details in delivery. Hands-on circuit designer with proficient system level understanding of different IPs. Specialize in mm-wave, RF and analog circuit design for wireless and wireline applications, including mm-wave power amplifiers, high-performance RX and TX, front-end passive components and analog building blocks.
Yi Zhao’s Current Industry Apple
Yi
Zhao’s Prior Industry
Nxp Semiconductors
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Ibm
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Marvell Semiconductor
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Apple
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Work Experience

Apple
RFIC Design Engineer/Manager
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Marvell Semiconductor
Staff RFIC Design Engineer
Fri Nov 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Benchmark Circuit Designer
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
RF and analog designer
Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
Intern as RF and analog designer
Sun Apr 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)