
Yongkee Kwon
<Aug.'15:Aug.'20> @UT Austin For the past five years at The University of Texas at Austin, I've not only learned... | South Korea
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Yongkee Kwon’s Location South Korea
Yongkee Kwon’s Expertise <Aug.'15:Aug.'20> @UT Austin For the past five years at The University of Texas at Austin, I've not only learned about lots of fundamentals of computer architecture, but also explored programming models and runtime systems as I planned before I joined LPH (Locality Parallelism and Hierarchy) Architecture Group, led by Dr. Mattan Erez. At (SK) hynix, I was privileged to get involved in very early stage of 3D stacked memory, which brought me to think about processing-[innear]-memory even before it's renaissance in academia. To that end, I'd like myself to be able to answer not merely how to architect but also how to program such a system, motivating my Ph.D. study as stated above. For that purpose, I attempted to explore parallel, concurrent, and perhaps asynchronous programming models. Those that I spent some time on include: Legion/Regent, Containment Domains, HSA Foundation/RoCm, Chapel, X10, Cuda, OpenMP, MPI, C++20 coroutines, golang, ponylang, thread/compute migraitions, active messages and many graph analytics DSLs/frameworks for both shared memory machines and distributed systems. I've focused mostly on modern architectures and contemporary programming models and runtime systems for my research. However, I found myself so exited with learning and revisiting lots of forward looking proposals and research in the past (including data flow machines). There is nothing really new and virtually everything old is new again, particularly for this interesting time being as an architect. <Jul.'06: Aug.'15> @SK hynix Design: Advanced DRAM design and TSV-stacked memory design Architecture and algorithm exploration: Memory Controller, Performance Evaluation, Workload characterization, Full system simulator, Linux instrumentation, Memory-sub system architecture Research: Memory channel devices, DRAM scaling challenges, Characterization and fault modeling, DRAM failures at the field, SSD architecture, PCM architecture & algorithms, File system for SCM, Error control & signal processing, Memory scheduling for SoC Industry-Academia joint research: mostly in computer architecture, with more than a dozen labs Joint Development with Intel, AMD and IBM, (former) HMC consortium protocol committee member Tools and Techniques: C, C++, Matlab, OCaml Cadence Opus, HSpice/HSIM, Xilinx ISE Pin (Intel), Simics, GEM5, SoC Designer(Carbon Design System) Award: Outstanding engineer '12 (CEO recognition)
Yongkee Kwon’s Current Industry Sk Hynix
Yongkee
Kwon’s Prior Industry
Sk Hynix America
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Sk Hynix
Principal Engineer And Project Leader
Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Sk Hynix
Principal Engineer
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Sk Hynix
Senior Research Staff
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Sk Hynix
Research Staff
Sat Jul 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Sk Hynix America
Principal Engineer and Project Leader
— Present