
Yue Zhang
Signal and power integrity (SI/PI) engineer with 8 years of industry experience in simulation and analysis of package,... | San Francisco Bay Area, San Francisco Bay Area, United States
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Yue Zhang’s Emails yz****@ga****.edu
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Yue Zhang’s Location San Francisco Bay Area, San Francisco Bay Area, United States
Yue Zhang’s Expertise Signal and power integrity (SI/PI) engineer with 8 years of industry experience in simulation and analysis of package, board, and systems Proven track records as tech lead for SI/PI from concept to prototyping to mass production Strong cross-functional communication skills regarding circuit design, system physical design, PCB/package layout design, EMC, de-sense, and bench/factory validation Hands-on experience in simulation and loss budgeting for high-speed interfaces including LPDDR, USB4, USB2, PCIe4, DP, and NAND and low-speed IO including SPMI and SPI In-depth knowledge of end-to-end power integrity analysis including VRM, board and package, routing optimization, and decoupling cap optimization Experience with bring-up support and debugging using TDR, waveforms, and internal eye; expertise in defining high-speed measurement methodology and waveform correlation Owner of factory testing station for voltage shmoo as the final metric for system margin Experience in working with vendors for spec definition and new technology development Key Technical Skills: Engineering Software: Cadence APD/Concept, ANSYS Mechanical/Thermal/Fluent, PowerDC, SIWave, Q3D, LTspice, ADS, Virtuoso, HFSS Technologies: Flip-chip, 2.5D/3D ICs, wire-bonding, SMT, CMOS/MEMS processing Programming: Python, Java, MATLAB
Yue Zhang’s Current Industry Apple
Yue
Zhang’s Prior Industry
Institute Delectronique De Microelectronique Et De Nanotechnologie
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Georgia Institute Of Technology
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Oracle
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Apple
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Work Experience

Apple
Lead SIPI Engineer
Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Apple
Senior SIPI engineer
Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Oracle
Senior Hardware Engineer
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Georgia Institute Of Technology
Graduate Research Assistant
Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Institute Delectronique De Microelectronique Et De Nanotechnologie
Research Assistant
Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)